參數(shù)資料
型號(hào)： T7288
廠商： Lineage Power
英文描述： CEPT/E1 Line Interface(CEPT/E1 線接口)
中文描述： CEPT/E1線路接口（CEPT/E1線接口）
文件頁(yè)數(shù)： 10/22頁(yè)
文件大?。?/td> 432K
代理商： T7288
Data Sheet
January 1998
T7288 CEPT/E1 Line Interface
10
Lucent Technologies Inc.
Overview
(continued)
Receive Converter
(continued)
Notes:
Equivalent binary content of input signal: 1000.
Jitter input amplitude = 0.1 U.I. peak-to-peak.
Figure 8. Receive Jitter Transfer Function
–20
0.1
100
FREQUENCY (kHz)
0
–5
–10
–15
10
T7288 MEASURED
1
36
G.735–G.739 SPECIFICATION
(100k, –8.4 dB)
–20 dB/DECADE
(36k, 0.5 dB)
2
Digital Logic
The logic provides alarms, optional HDB3 coding, blue
signal (AIS) insertion circuits, and maintenance loop-
backs. It also optionally performs dual-rail to single-rail
conversion of the data and provides an alternate logic
polarity (logic mode 2) in dual-rail mode for receive
clock and receive and transmit data.
Single-Rail/Dual-Rail Interface and Alternate
Logic Mode
The T7288 device supports either single-rail or dual-rail
operation by setting the control pin
SR
/DR. In the sin-
gle-rail mode (
SR
/DR = 0), the T7288 receiver converts
bipolar input signals (T1, R1) to a unipolar output signal
on RDATA. The T7288 transmitter converts a unipolar
input signal on TDATA to a balanced bipolar data signal
on pins T2 and R2. If desired, the HDB3 control pin can
be used to set HDB3 encoding/decoding. Violation
information is available on output pin VIO.
In the dual-rail mode (
SR
/DR = 1), the T7288 receiver
converts bipolar input signals (T1, R1) to p-rail and
n-rail, nonreturn-to-zero output data on pins RPDATA
and RNDATA, respectively. The T7288 transmitter con-
verts nonreturn-to-zero p-rail and n-rail input data on
pins TPDATA and TNDATA, respectively, to a balanced
bipolar data signal on pins T2 and R2. In the dual-rail
mode, HDB3 encoding/decoding and bipolar violation
output functions are unavailable.
In the dual-rail mode, an alternate-logic polarity mode
is available via control pin FLM. If FLM = 1, the T7288
device operates in logic mode 2; RCLK is inverted with
respect to logic mode 1, and input and output data
(TPDATA, TNDATA, RPDATA, and RNDATA) are active-
low (see Figures 10—13).
Internal pull-downs on signals
SR
/DR and FLM set
default operation to single-rail, logic mode 1 (see
Table 4).
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