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參數資料
| 型號： | T4312816B-6SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| 中文描述： | 8米× 16 SDRAM的2米x 16Bit的X 4Banks同步DRAM |
| 文件頁數： | 3/70頁 |
| 文件大小： | 688K |
| 代理商： | T4312816B-6SG |
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TE
CH
tm
Pin Descriptions
(Table 1. Pin Details )
Symbol
Type
CLK
Input
T4312816B
TM Technology Inc. reserves the right
P. 3
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
Description
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the output
registers.
Clock Enable:
CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes
low synchronously with clock(set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen as
long as the CKE remains low. When all banks are in the idle state, deactivating the clock
controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except
after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
Bank Select:
BA0,BA1 input select the bank for operation.
CKE
Input
BA1
0
0
1
1
BA0
0
1
0
1
Select Bank
BANK #A
BANK #B
BANK #C
BANK #D
BA0,BA1
Input
A0-A11
Input
Address Inputs:
A0-A11 are sampled during the BankActivate command (row address A0-
A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge)
to select one location out of the 2M available in the respective bank. During a Precharge
command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The
address inputs also provide the op-code during a Mode Register Set command.
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction with
the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and
CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or
the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH,"
the BankActivate command is selected and the bank designated by BS is turned on to the
active state. When the WE# is asserted "LOW," the Precharge command is selected and the
bank designated by BS is switched to the idle state after the precharge operation.
Column Address Strobe:
The CAS# signal defines the operation commands in conjunction
with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is
held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS#
"LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH."
Write Enable:
The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used
to select the BankActivate or Precharge command and Read or Write command.
Data Input/Output Mask:
Controls output buffers in read mode and masks
Input data in write mode.
Input / Output
Data I/O:
The DQ0-15 input and output data are synchronized with the positive edges of
CLK. The I/Os are maskable during Reads and Writes.
-
No Connect:
These pins should be left unconnected.
Supply
DQ Power:
Provide isolated power to DQs for improved noise immunity. ( 3.3V
±
0.3V )
Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.( 0 V )
Supply
Power Supply:
+3.3V
±
0.3V
Supply
Ground
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
LDQM,
UDQM
DQ0-DQ15
Input
NC/RFU
VDDQ
VSSQ
VDD
VSS
相關PDF資料 |
PDF描述 |
|---|---|
| T4312816B-7S | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-7SG | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T431616A | 1M x 16 SDRAM |
| T431616A-7C | 1M x 16 SDRAM |
| T431616A-7CI | 1M x 16 SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| T4312816B-7S | 制造商:TMT 制造商全稱:TMT 功能描述:8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4314 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
| T431616A | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM |
| T431616A-7C | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM |
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