- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361343 > T4312816B-6SG (TM Technology, Inc.) 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | T4312816B-6SG |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| 中文描述： | 8米× 16 SDRAM的2米x 16Bit的X 4Banks同步DRAM |
| 文件頁(yè)數(shù)： | 12/70頁(yè) |
| 文件大小： | 688K |
| 代理商： | T4312816B-6SG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)
TE
CH
tm
T4312816B
TM Technology Inc. reserves the right
P. 12
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
This field specifies the number of clock cycles from the assertion of the Read command to the first read data.
The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value
satisfying the following formula must be programmed into this field.
t
CAC
(min)
≤
CAS# Latency X t
CK
A6
A5
A4
0
0
0
0
0
1
0
1
0
0
1
1
1
X
X
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
A8
A7
Test Mode
0
0
normal mode
0
1
Vendor Use Only
1
X
Vendor Use Only
Write Burst Length (A9)
This bit is used to select the burst write length.
A9
Write Burst Length
0
Burst
1
Single Bit
No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low).
This prevents unwanted commands from being registered during idle or wait states.
10 Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is
only effective in a read/write burst without the auto precharge function. The terminated read burst ends after a
delay equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the
following figure.
T0
T 1
T2
T3
CAS# Latency
Reserved
Reserved
2 clocks
3 clocks
Reserved
9
CLK
COMMAND
T4
T5
T6
T7
T8
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Burst Stop
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
The burst ends after a delay equal to the CAS# latency.
Termination of a Burst Read Operation
(Burst Length
4, CAS# Latency = 2, 3)
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Burst Stop
CAS# latency= 2, 3
DQ's
DIN A0
DIN A1
DIN A2
don't care
Input data for the Write is masked.
Termination of a Burst Write Operation
(Burst Length = X, CAS# Latency = 1, 2, 3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T4312816B-7S | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-7SG | 8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T431616A | 1M x 16 SDRAM |
| T431616A-7C | 1M x 16 SDRAM |
| T431616A-7CI | 1M x 16 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T4312816B-7S | 制造商:TMT 制造商全稱:TMT 功能描述:8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4312816B-7SG | 制造商:TMT 制造商全稱:TMT 功能描述:8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM |
| T4314 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIANGULAR TYPE |
| T431616A | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM |
| T431616A-7C | 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。