
2-2
Functional Description
Unlike previous generation devices, the SCSI core can be controlled by
the integrated DMA core through a high level logical interface.
Commands controlling the SCSI core are fetched out of the main host
memory. These commands instruct the SCSI core to Select, Reselect,
Disconnect, Wait for a Disconnect, Transfer Information, Change Bus
Phases and in general, implement all aspects of the SCSI protocol.
2.1.1 DMA Core
The DMA core is a bus master DMA device that directly attaches to
68030 and 68040 processors, and to other processors (80386, 80486,
etc.) with minimum logic.
The SYM53C710 supports 32-bit memory and automatically supports
misaligned DMA transfers. A 64-byte FIFO allows the SYM53C710 to
support one, two, four, or eight longwords to be burst across the memory
bus interface. This DMA interface does not support dynamic bus sizing.
The DMA core is tightly coupled to the SCSI core through the SCRIPTS
processor which supports uninterrupted scatter/gather memory
operations.
2.2 SCRIPTS Processor
The SCRIPTS processor is a special high speed processor optimized for
SCSI protocol. It allows both DMA and SCSI instructions to be fetched
from host memory. Algorithms written in SCSI SCRIPTS can control the
actions of the SCSI and DMA cores and are executed from 32-bit system
memory. Complex SCSI bus sequences are executed independently of
the host CPU.
The SCRIPTS processor can begin a SCSI I/O operation in
approximately 500 ns. This compares with 2–8 ms required for traditional
intelligent host adapters. The SCRIPTS processor offers performance
and customized algorithms. Algorithms may be designed to tune SCSI
bus performance, to adjust to new bus device types (i.e. scanners,
communication gateways, etc.) or to incorporate changes in the
SCSI-2/SCSI-3 logical bus definitions without sacrificing I/O
performance.