參數(shù)資料
型號(hào)： STA304A
廠商： 意法半導(dǎo)體
英文描述： 20 POS IMAGE SENSOR SOCKT
中文描述： 數(shù)字音頻處理器多通道的DDX⑩
文件頁(yè)數(shù)： 25/30頁(yè)
文件大?。?/td> 338K
代理商： STA304A
25/30
STA304A
12.10Configuration Register B (CRB) : add. 5Ch
NOTE: Power-on default values will configure serial input interface as I2S Slave and the output interface as I2S Master.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
I2SO_M
SbLSb
I2SO_LR
CK_Master
I2SO_LR
CK_Pol
I2SO_BC
K_Master
I2SO_BI
CK_Pol
I2SO_Ali
gn_2
I2SO_Ali
gn_1
I2SO_Ali
gn_0
I2SI_MS
bLSb
I2SI_LR
CK_Master
I2SI_LR
CK_Pol
I2SI_BC
K_Master
I2SI_BIC
K_Pol
I2SI_Alig
n_2
I2SI_Alig
n_1
I2SI_Alig
n_0
BIT
R/W
RST
NAME
DESCRIPTION
0
R/W
1
I2SI_Align_0
I2S (Input) Alignement. Using these bits the word alignement can be
adjusted with respect to the LRCK edges. Please refer to the related
paragraph for more details. The default value is mode 1.
1
R/W
0
I2SI_Align_1
2
R/W
0
I2SI_Align_2
3
R/W
1
I2SI_BICK_Pol
I2S (Input) BICK Polarity. This bit should be configured according to the
used serial protocol. In order to sample incoming data on the rising
edge (data changes on the falling edge) this bit should be set to 1. Set
to 0 to reverse the sampling edge.
4
R/W
0
I2SI_BCK_Master
I2S (Input) Master/Slave Selection. The I2S input interface can be
configured as both master or slave: if the master mode is selected (1)
the BICK line will be an output (64 x 48KHz fixed). Otherwise (0) slave
mode is selected and this line is an input.
5
R/W
0
I2SI_LRCK_Pol
I2S (Input) LRCK Polarity. Set to 0 to receive LEFT samples when
LRCK is low, 1 otherwise.
6
R/W
0
I2SI_LRCK_Master
I2S (Input) Master/Slave Selection. The I2S input interface can be
configured as both master or slave: if the master mode is selected (1)
the LRCK line will be an output (48KHz fixed). Otherwise (0) slave mode
is selected and this line is an input (continuous frequency between
32KHz and 96KHz).
7
R/W
1
I2SI_MSbLSb
I2S (Input) MSb/LSb Selection. Use this bit to select how the sample word is
received by the I2S input interface: set to 0 to configure as LSb first, 1 MSb first.
8
R/W
1
I2SO_Align_0
I2S (Output) Alignemt. Using these bits the word alignement can be
adjusted with respect to the LRCK edges. Please refer to the related
paragraph for more details. The default value is mode 1.
9
R/W
0
I2SO_Align_1
10
R/W
0
I2SO_Align_2
11
R/W
1
I2SO_BICK_Pol
I2S (Output) BICK Polarity. This bit should be configured according to
the used serial protocol. In order to sample outcoming data on the rising
edge (data changes on the falling edge) this bit should be set to 1. Set
to 0 to reverse the sampling edge.
12
R/W
1
I2SO_BCK_Master
I2S (Output) Master/Slave Selection. The I2S output interface can be
configured as both master or slave: if the master mode is selected (1)
the BICK line will be an output (64 x 48KHz fixed). Otherwise (0) slave
mode is selected and this line is an input.
13
R/W
0
I2SO_LRCK_Pol
I2S (Output) LRCK Polarity. Set to 0 to transmit LEFT samples when
LRCK is low, 1 otherwise.
14
R/W
1
I2SO_LRCK_Master
I2S (Output) Master/Slave Selection. The I2S output interface can be
configured as both master or slave: if the master mode is selected (1)
the LRCK line will be an output. Otherwise (0) slave mode is selected
and this line is an input. In any case the frequency is fixed at 48 kHz
15
R/W
1
I2SO_MSbLSb
I2S (Output) ) MSb/LSb Selection. Use this bit to select how the sample
word is transmitted by the I2S output interface: set to 0 to configure as
LSb first, 1 MSb first.
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