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參數(shù)資料
| 型號： | STA304A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 20 POS IMAGE SENSOR SOCKT |
| 中文描述： | 數(shù)字音頻處理器多通道的DDX⑩ |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 338K |
| 代理商： | STA304A |
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STA304A
and read or write mode.
The 7 most significant bits are the device address identifier, corresponding to the I
2
C bus definition.
In STA304A the I
2
C interface has two device address depending on SA pin configuration 0011110 when SA =
0, and 0011111 when SA = 1.
The 8th bit (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After
a START condition the STA304A identifies on the bus the device address and, if a match is found, it acknowl-
edges the identification on SDA bus during the 9th bit time. The following byte after the device identification byte
is the internal space address.
11.3WRITE OPERATION
Following a START condition the master sends a device select code with the RW bit set to 0. The STA304A
acknowledges this and waits for the byte of internal address. After receiving the internal bytes address the
STA304A again responds with an acknowledge.
11.3.1Byte write
In the byte write mode the master sends one data byte, this is acknowledged by STA304A. The master then
terminates the transfer by generating a STOP condition.
11.3.2Multibyte write
The multibyte write mode can start from any internal address. The transfer is terminated by the master gener-
ating a STOP condition.
Figure 13. Write Mode Sequence
Figure 14. Read Mode Sequence
DEV-ADDR
ACK
START
D98AU825B
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
BYTE
WRITE
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
MULTIBYTE
WRITE
DATA IN
ACK
DEV-ADDR
ACK
START
D98AU826A
RW
DATA
NO ACK
STOP
CURRENT
ADDRESS
READ
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
STOP
RANDOM
ADDRESS
READ
DATA
NO ACK
START
RW
DEV-ADDR
ACK
START
DATA
ACK
DATA
ACK
STOP
SEQUENTIAL
CURRENT
READ
DATA
NO ACK
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
SEQUENTIAL
RANDOM
READ
DATA
ACK
START
RW
DATA
ACK
NO ACK
STOP
DATA
RW=
HIGH
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