參數(shù)資料
型號(hào)： STA304A
廠商： 意法半導(dǎo)體
英文描述： 20 POS IMAGE SENSOR SOCKT
中文描述： 數(shù)字音頻處理器多通道的DDX⑩
文件頁(yè)數(shù)： 23/30頁(yè)
文件大?。?/td> 338K
代理商： STA304A
23/30
STA304A
12.9Configuration Register A (CRA) : add. 5Ah
NOTE: In TEST_MODE -> PLL_Bypass = 0.
Table 1. SRC Threshold
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SRC_By
pass
DRLL_d
bg
SRC_TH
R_1
SRC_TH
R_0
SPDIF_
Mode
I2S_SP
DIF_Sel
MCKOU
T_Mode
PLL_By
pass
PLL_Fac
tor
DDX_P
wrMode
DDX_ZD
_Enable
DDX_Rst
DDX_Ga
in_1
DDX_Ga
in_0
I2SI_DBU
FF_Mode
AC97_F
C_Mode
BIT
0
R/W
R/W
RST
0
NAME
DESCRIPTION
AC97_FC_Mode
AC’97 Full Compliant Mode (0 to enable). When in FC mode any read
of registers will return only valid bits: bits marked as ‘reserved’ by
AC’97 v2.0 specification will return 0, regardless of the RAM
contents.
Enable DoubleBuffer mode for the I2S input interface (write1 to
enable this option) . This is strongly required if this interface is
operated in slave mode at 48KHz, synchronous with the input source.
In this condition also Sample Rate Converter Bypass is suggested to
omprove performances
DDX Gain setting (LSb/MSb). These two bits, concatenated, will set
the DDX stage gain and the compression as shown in Table 1.
(These setting is active only if bit 15 reg 62h is 0)
DDX Reset (active high)
DDX Zero Detect feature. If this bit is 1 the feature is enabled.
DDX Power Mode (TRUTH Table). Using this bit it is possible to select
the truth table used by the DDX digital output stage (1 = ST standard)
PLL Factor (x2 or x8). It should be used according to the input
frequency provided to the device: 1 (x8) when 6.144 MHz are
provided, 0 (x2) when 24.576 MHz.
PLL Bypass. Setting this bit to 0 will bypass the PLL; internal master
clock will be directly connected to XTI pin.
MckOut mode: 12.288 MHz (1) or 24.576 MHz (0).
I2S - S/PDIF Selector. Select the input source: set to 0 for I2S input, 1
for S/PDIF input.
S/PDIF Mode. Set to 0 to select Analog mode, 1 to select Digital
mode.
Sample Rate threshold (LSb/MSb). These bits are used to select the
threshold frequency enabling the SRC anti-alias filter.
Table 2 shows the threshold selections.
DRLL Debug Mode. When this mode is activated (1) the DRLL digital
ratio is latched on the output channels instead of the audio data.
SRC Bypass. Setting this bit to 1 the SRC block can be bypassed and
the selected input I/F is directly connected to the DSP
1
R/W
0
I2SI_DBUFF_Mode
2
3
R/W
R/W
0
0
DDX_Gain_0
DDX_Gain_1
4
5
6
R/W
R/W
R/W
1
1
1
DDX_Rst
DDX_ZD_Enable
DDX_PwrMode
7
R/W
0
PLL_Factor
8
R/W
1
PLL_Bypass
9
R/W
R/W
0
0
MCKOUT_Mode
I2S_SPDIF_Sel
10
11
R/W
0
SPDIF_Mode
12
R/W
1
SRC_THR_0
13
14
R/W
R/W
0
0
SRC_THR_1
DRLL_dbg
15
R/W
0
SRC_Bypass
SRC_THR_0
SRC_THR_1
Threshold Frequency
0
0
INACTIVE
0
1
58.875 to 61.125kHz
1
0
78.973 to 81.000kHz
1
1
always active
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