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參數(shù)資料
| 型號： | STA304A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 20 POS IMAGE SENSOR SOCKT |
| 中文描述： | 數(shù)字音頻處理器多通道的DDX⑩ |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 338K |
| 代理商： | STA304A |
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STA304A
10/30
5.0 SAMPLE RATE CONVERTER
The sample rate converter resamples the selected input data source in order to send to the DSP an audio
stream with a fixed frequency of 48 KHz. The following picture show the basic architecture.
Figure 4.
The selection between X2 Fir interpolation or direct antialiasing Filter on input data is made automatically by the
threshold selector block. If the input sampling frequency (measured by DRLL) is high than the SRC threshold
(see Table 2 section 12.9), the direct antialising filter is selected, otherwise if the input frequency is lower than
the SRC threshold, the X2 FIR filter is added the data path. A 1kHz hysteresis is fixed around the SRC threshold
nominal values of tab. 2 section 12.9, to prevent unstable oscillations. In figure 5 the DRLL lock phase is shown
for 32kHz,44.1kHz, 48kHz and 96kHz input frequency. Note that only after this phase (including the flat part of
the graph) the SRC performances are in spec.
Figure 5. DRLL lock delay
Interpolation
FIR x2
Anti-Alias
FILT
Interpolation
FIR x2
2xFs
Fs
Fs
DATA_IN
Sinc 6
Async.
DRLL
LRCK_IN
Thresh.
Selector
RATIO
4xFs or2xFs
DATA_OUT
48KHz
0
0.05
0.1
0.15
0.2
0.25
0
1
2
3
4
5
6
7
8
9
10x 10
4
Second
E
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