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| 型號： | ST7PL05Y0MB |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 96/108頁 |
| 文件大小： | 2098K |
| 代理商： | ST7PL05Y0MB |
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ST7L0
88/108
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
TA = -40 to +105°C, unless otherwise specified
Notes:
1. Data based on characterization results, not tested in production.
2. The IIO current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 73 and the
sum of IIO (I/O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
VILmax and VDD
4. To guarantee the reset of the device, a minimum pulse must be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
5. Guaranteed by design, not tested in production
Figure 64. RESET pin protection1)
Notes:
1. The reset network protects the device against parasitic resets. The output of the external reset circuit must have an
open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (watchdog).
- Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in section 13.9.1 on page 88. Otherwise the reset will not be taken into account internally.
- Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in section 13.2.2
2. Please refer to “Illegal Opcode Reset” on page 69 for more details on illegal opcode reset conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
VSS -0.3
0.3 x VDD
V
VIH
Input high level voltage
0.7 x VDD
VDD +0.3
Vhys
Schmitt trigger voltage
hysteresis1)
2
VOL
Output low level voltage
VDD =5V
IIO = +5mA
TA ≤ 85°C
TA ≤ 105°C
0.5
1.05)
1.25)
IIO = +2mA
TA ≤ 85°C
TA ≤ 105°C
0.2
0.45)
0.55)
RON
Pull-up equivalent resistor3)1)
VDD = 5V
20
40
80
k
tw(RSTL)ou
t
Generated reset pulse duration
Internal reset sources
30
s
th(RSTL)in
External reset pulse hold time4)
20
tg(RSTL)in
Filtered glitch duration
200
ns
0.01
F
EXTERNAL
RESET
CIRCUIT
USER
ST72XXX
PULSE
GENERATOR
Filter
RON
VDD
INTERNAL
RESET
WATCHDOG
ILLEGAL OPCODE2)
1
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