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參數(shù)資料
| 型號(hào)： | ST7PL05Y0MB |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 101/108頁 |
| 文件大小： | 2098K |
| 代理商： | ST7PL05Y0MB |
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ST7L0
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ADC CHARACTERISTICS (Cont’d)
Figure 69. RAIN max. vs fADC with CAIN =0pF
1)
Figure 70. Recommended CAIN/RAIN values
2)
Notes:
1.CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC must be reduced.
2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization and to allow
the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4 MHz.
13.11.0.1 General PCB Design Guidelines
To obtain best results, some general design and
layout rules must be followed when designing the
application PCB to shield the noise-sensitive, ana-
log
physical
interface
from
noise-generating
CMOS logic signals.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.
0
5
10
15
20
25
30
35
40
45
010
30
70
CPARASITIC (pF)
Max.
R
AI
N
(Kohm)
4 MHz
2 MHz
1 MHz
0.1
1
10
100
1000
0.01
0.1
1
10
fAIN(KHz)
Max.
R
AI
N
(Kohm)
Cain 10 nF
Cain 22 nF
Cain 47 nF
1
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