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參數(shù)資料
| 型號： | ST7PL05Y0MB |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 37/108頁 |
| 文件大?。?/td> | 2098K |
| 代理商： | ST7PL05Y0MB |
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ST7L0
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POWER SAVING MODES (Cont’d)
9.4.2 HALT Mode
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when active halt mode is disa-
bled.
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 29) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
CPU cycle delay is used to stabilize the oscillator.
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up (see Figure 22).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In HALT mode, the main oscillator is turned off
causing all internal processing to stop, including
the operation of the on-chip peripherals. All periph-
erals are not clocked except the ones which get
their clock supply from another clock generator
(such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 15.1 on page 97 for more details).
Figure 21. HALT Timing Overview
Figure 22. HALT Mode Flowchart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 7, “Interrupt Mapping,” on page 29 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
5. If the PLL is enabled by option byte, it outputs
HALT
RUN
256 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
[Active Halt disabled]
HALT INSTRUCTION
RESET
INTERRUPT3)
Y
N
Y
CPU
OSCILLATOR
PERIPHERALS2)
IBIT
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
X4)
ON
CPU
OSCILLATOR
PERIPHERALS
IBITS
ON
X4)
ON
256 CPU CLOCK CYCLE
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT1)
0
WATCHDOG
RESET
1
(Active Halt disabled)
1
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