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參數(shù)資料
| 型號： | ST7PL05Y0MB |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 29/108頁 |
| 文件大?。?/td> | 2098K |
| 代理商： | ST7PL05Y0MB |
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ST7L0
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SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d)
7.4.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It is pulled low by
external circuitry to reset the device. See Electrical
Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
7.4.3 External Power-On RESET
To start up the microcontroller correctly, the user
must ensure by means of an external reset circuit
that the reset signal is held low until VDD is over
the minimum level specified for the selected fOSC
frequency.
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC net-
work connected to the RESET pin.
7.4.4 Internal Watchdog RESET
A RESET sequence is generated by a internal
Watchdog counter overflow.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
1
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