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| 型號(hào)： | ST7FDALIF2M6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI |
| 中文描述： | 8位單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，定時(shí)器，SPI和大理微控制器 |
| 文件頁(yè)數(shù)： | 29/141頁(yè) |
| 文件大?。?/td> | 2175K |
| 代理商： | ST7FDALIF2M6 |
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7.6 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Note:
A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to
section 12.2.1 on page 97
for further details.
7.6.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
ates a static reset when the V
DD
supply voltage is
below a V
IT-(LVD)
reference value. This means that
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The V
IT-(LVD)
reference value for a voltage drop is
lower than the V
IT+(LVD)
reference value for power-
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
V
DD
is below:
– V
IT+(LVD)
when V
DD
is rising
– V
IT-(LVD)
when V
DD
is falling
The LVD function is illustrated in
Figure 16
.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum V
DD
value (guaranteed for
the oscillator frequency) is above V
IT-(LVD)
, the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes
:
The LVD allows the device to be used without any
external RESET circuitry.
The LVD is an optional function which can be se-
lected by option byte.
It is recommended to make sure that the V
DD
sup-
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
Figure 16. Low Voltage Detector vs Reset
V
DD
V
IT+
(LVD)
V
IT-
(LVD)
RESET
V
hys
1
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