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參數(shù)資料
| 型號： | ST7FDALIF2M6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI |
| 中文描述： | 8位單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，定時器，SPI和大理微控制器 |
| 文件頁數(shù)： | 113/141頁 |
| 文件大?。?/td> | 2175K |
| 代理商： | ST7FDALIF2M6 |
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ST7DALI
113/141
EMC CHARACTERISTICS
(Cont’d)
13.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
13.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). This test conforms to the JESD22-
A114A/A115A standard.
Absolute Maximum Ratings
Notes:
1. Data based on characterization results, not tested in production.
13.7.3.2 Static and Dynamic Latch-Up
■
LU
: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the application note
AN1181.
■
DLU
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to the
application note AN1181.
Electrical Sensitivities
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
Symbol
Ratings
Conditions
Maximum value
1)
Unit
V
ESD(HBM)
Electro-static discharge voltage
(Human Body Model)
T
A
=
+25°C
4000
V
Symbol
Parameter
Conditions
Class
1)
LU
DLU
Static latch-up class
Dynamic latch-up class
T
A
=
+25°C
V
DD
=
5.5V, f
OSC
=
4MHz, T
A
=
+25°C
A
A
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