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參數(shù)資料
| 型號(hào)： | ST72T85A5Q6 |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤(pán)，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口 |
| 文件頁(yè)數(shù)： | 83/117頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
5.3 ST7 INSTRUCTION SET
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Using a pre-byte
The instructions are described with one to four op-
codes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 op-codes), three dif-
ferent prebyte opcodes are defined. These preb-
ytes modify the meaning of the instruction they
precede.
The whole instruction becomes:
PC-2
End of previous instruction
PC-1
Prebyte
PC
Op-code
PC+1
Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90Replace an X based instruction using im-
mediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct
bit, or direct relative addressing mode to
an instruction using the corresponding in-
direct addressing mode.
It also changes an instruction using X in-
dexed addressing mode to an instruction
using
indirect
mode.
PIY 91 Replace an instruction using X indirect in-
dexed addressing mode by a Y one.
X
indexed
addressing
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
RSP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
RET
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Code Condition Flag modification
SIM
RIM
SCF
RCF
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