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參數(shù)資料
| 型號(hào)： | ST72T85A5Q6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口 |
| 文件頁(yè)數(shù)： | 11/117頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
I
2
C
CR: Control Register
SR1: Status Register 1
SR2: Status Register 2
CCR: Clock Control Register
OAR1: Own Address Register 1
OAR2: Own Address Register 2
DR: Data Register
00h
00h
00h
00h
00h
00h
00h
R/W Register
Read Only Register
Read Only Register
R/W Register
R/W Register
R/W Register
R/W Register
RESERVED
Timer A
Control Reg2
Control Reg1
Status Reg
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low RegisteR
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
00h
00h
XXh
XXh
XXh
XXh
XXh
FFh
FCh
00h
00h
XXh
XXh
XXh
XXh
R/W Register
R/W Register
Read Only Register
Read Only Register
Read Only Register
R/W Register
R/W Register
Read Only Register
Read Only Register
Read Only Register
Read Only Register
Read Only Register
Read Only Register
R/W Register
R/W Register
RESERVED
Timer B
Control Reg2
Control Reg1
Status Reg
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
SCSR: Status Register
SCDR: Data Register
SCBRR: Baud Rate Register
SCCR1: Control Register 1
SCCR2: Control Register 2
PSCBRR: Receive Baud Rate Reg
Reserved
PSCBRT: Transmit BaudRateReg
00h
00h
XXh
XXh
XXh
XXh
XXh
FFh
FCh
00h
00h
XXh
XXh
XXh
XXh
R/W Register
R/W Register
Read Only Register
Read Only Register
Read Only Register
R/W Register
R/W Register
Read Only Register
Read Only Register
Read Only Register
Read Only Register
Read Only Register
Read Only Register
R/W Register
R/W Register
Read Only Register
R/W Register
R/W Register
R/W Register
R/W Register
R/W Register
Reserved ST use
R/W Register
SCI
SCI Prescaler
1100000xb
XXh
00x----xb
XXh
00h
00h
---
00h
RESERVED
RESERVED
RDS Filter
RDS FI1
RDS FI2
R/W Register
R/W Register
Address
Block
Register name
Reset
Status
Remarks
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