參數(shù)資料
型號(hào)： ST72T85A5Q6
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述： 8位微控制器48,000鐵路發(fā)展策略光盤(pán)，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口
文件頁(yè)數(shù)： 20/117頁(yè)
文件大?。?/td> 748K
代理商： ST72T85A5Q6
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ST7285C
3.5 INTERRUPTS
A list of interrupt sources is given inTable 5below,
together with relevant details for each source. In-
terrupts are serviced according to their order ofpri-
ority, starting with I0, which has the highest priori-
ty, and so to I11, which has the lowest priority.
The following list describes the origins for each in-
terrupt level:
– I0 connected to Software Interrupt (TRAP)
– I1 connected to Port G3
– I2 connected to Port F0, F1, F2, F3
– I3 connected to SPI A
– I4 connected to Timer A
– I5 connected to GBS interrupt
– I6 connected to Timer B
– I7 connected to SPI B
– I8 connected to SCI
– I9 connected to Ports D4, D5
– I10 connected to Ports C4, C5
– I11 connected to I
2
C
Exit from HALT mode may only be triggered by an
External Interrupt on one of the following ports:
C4(I10), C5(I10), D4(I9), D5(I9), F0(I2), F1(I2),
F2(I2), F3(I2) and G3(I1).
If more than one input pin of a group connected to
the same interrupt line is selected simultaneously,
these will be logically ORed.
Table 5. Interrupt Mapping
Interrupt
source
-
I0
I1
I2
I3
“
I4
“
“
“
“
Vector
Address
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
“
FFF4h-FFF5h
“
“
“
“
Interrupts
Register
Flag
name
N/A
N/A
N/A
N/A
SPIF1_A
MODF1_A
ICF1_A
OCF1_A
ICF2_A
OCF2_A
TOF_A
VSI
CNI
ICF1_B
OCF1_B
ICF2_B
OCF2_B
TOF_B
SPIF2_B
MODF1_B
TDRE
TC
RDRF
IDLE
OR
N/A
N/A
BTF
BERR
SSTOP
CPU
interrupts
RESET
TRAP
INT1
INT2
SPI_A
“
TIMER_A
“
“
“
“
Reset
Software
Ext. Interrupt (Port G3)
Ex. Interrupt (Ports F0, F1, F2, F3)
Transfer Complete
Mode Fault
Input Capture 1
Output Compare 1
Input Capture 2
Output Compare 2
Timer Overflow
N/A
N/A
N/A
N/A
SPI A Status
“
Timer A Status
“
“
“
“
I5
FFF2h-FFF3h
RDS Block Interrupt.
RDS GRP
GBS
I6
“
“
“
“
I7
“
I8
“
“
“
“
I9
I10
I11
“
“
FFF0h-FFF1h
“
“
“
“
FFEEh-FFEFh
“
FFECh-FFEDh
“
“
“
“
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
“
“
Input Capture 1
Output Compare 1
Input Capture 2
Output Compare 2
Timer Overflow
Transfer Complete
Mode Fault
Transmit Buffer Empty
Transmit Complete
Receive Buffer Full
Idle Line Detect
Overrun
Ext. Interrupt (Ports D4,D5)
Ext. Interrupt (Port C4, C5)
Byte Transmission Finished
Bus Error
Stop Detection
Timer B Status
“
“
“
“
SPI B Status
“
SCI Status
“
“
“
“
N/A
N/A
I
2
C Status
“
“
TIMER_B
“
“
“
“
SPI_B
“
SCI
“
“
“
“
INT9
INT10
I2C
I2C
I2C
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