參數(shù)資料
型號(hào): ST72F652R4T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, TQFP-64
文件頁數(shù): 89/160頁
文件大?。?/td> 974K
代理商: ST72F652R4T1
ST7265
34/160
POWER SUPPLY MANAGEMENT (Cont’d)
6.4.2.2 Switching from USB Mode to Stand-
Alone Mode
In USB Mode, when the user unplugs the USB ca-
ble, the voltage level drops on the USBVDD line.
The on-chip Power Supply Manager generates a
PLG interrupt when USBVDD reaches USBVIT-.
The user program then can finish the current
processing, and MUST generate a software RE-
SET.
Caution: Care should be taken as during this peri-
od the microcontroller clock is provided from the
PLL output. Functionality in this mode is not guar-
anteed for voltages below VPLLmin.
Software must ensure that the software RESET is
generated before VDD. drops below VPLLmin. Fail-
ing to do this will cause the clock circuitry to stop,
freezing the microcontroller operations.
Once the user program has executed the software
reset, the microcontroller goes into reset state and
all I/O ports go into floating input mode.
During and after this (software induced) reset
phase, the USBEN pin is put in high impedance by
hardware. It causes the USB SWITCH to be
turned OFF, so USBVDD is disconnected from
VDD. The PLL is automatically stopped and the in-
ternal frequency is provided by a division of the
crystal frequency. Refer to Figure 23.
The microcontroller is still powered by the residual
USBVDD voltage (higher than step-up converter
set output level). This VDD voltage decreases dur-
ing the reset phase until it reaches the step-up
converter set output voltage. At that time, step-up
converter resumes operation, and powers the ap-
plication.
Caution: In order to avoid applying excessive volt-
age to the Storage Media, a minimum delay must
be ensured during (and after if needed) the reset
phase, prior to switching ON the external STOR-
AGE switch. See Figure 24 and Figure 25.
1
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