參數(shù)資料
型號(hào)： ST72F652R4T1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, TQFP-64
文件頁數(shù)： 54/160頁
文件大?。?/td> 974K
代理商： ST72F652R4T1
ST7265
147/160
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.11.3 I
2C - Inter IC Control Interface
1) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
2) The maximum hold time of the START condition has only to be met if the interface does not stretch the
low period of SCL signal
Cb = total capacitance of one bus line in pF
I
2
C-Bus Timings
Parameter
Standard I
2
C
Fast I
2
C
Symbol
Unit
Min
Max
Min
Max
Bus free time between a STOP and START con-
dition
4.7
1.3
TBUF
ms
Hold time START condition. After this period,
the first clock pulse is generated
4.0
0.6
THD:STA
s
LOW period of the SCL clock
4.7
1.3
TLOW
s
HIGH period of the SCL clock
4.0
0.6
THIGH
s
Set-up time for a repeated START condition
4.7
0.6
TSU:STA
s
Data hold time
0 (1)
0.9(2)
THD:DAT
ns
Data set-up time
250
100
TSU:DAT
ns
Rise time of both SDA and SCL signals
1000
20+0.1Cb
300
TR
ns
Fall time of both SDA and SCL signals
300
20+0.1Cb
300
TF
ns
Set-up time for STOP condition
4.0
0.6
TSU:STO
ns
Capacitive load for each bus line
400
Cb
pF
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