參數(shù)資料
型號： ST72F652R4T1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, TQFP-64
文件頁數(shù)： 6/160頁
文件大?。?/td> 974K
代理商： ST72F652R4T1
ST7265
103/160
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.7.5 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
Bit 7 = SPIE
Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 6 = SPE
Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.7.4.7 Master Mode Fault).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.
Bit 5 = SPR2
Divider Enable.
This bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 29 Serial Periph-
eral Baud Rate.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4 = MSTR
Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.7.4.7 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
Bit 3 = CPOL
Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Note: The SPI must be disabled by resetting SPE
bit if CPOL is changed at the communication byte
boundaries.
Bit 2 = CPHA
Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bits 1:0 = SPR[1:0]
Serial Peripheral Rate.
These bits are set and cleared by software. Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
These 2 bits have no effect in slave mode.
Table 29. Serial Peripheral Baud Rate
70
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Serial Clock
SPR2
SPR1
SPR0
fCPU/4
100
fCPU/8
000
fCPU/16
0
1
fCPU/32
1
0
fCPU/64
0
1
0
fCPU/128
0
1
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