參數(shù)資料
型號(hào)： ST72F652R4T1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, TQFP-64
文件頁數(shù)： 132/160頁
文件大?。?/td> 974K
代理商： ST72F652R4T1
ST7265
73/160
USB INTERFACE (Cont’d)
Download Mode
IN transactions are managed the same way as in
normal mode (by software with the help of CTR in-
terrupt) but OUT transactions are managed by
hardware. This means that no CTR interrupt is
generated at the end of an OUT transaction and
the STAT_RX bits are set to valid by hardware
when the buffer is ready to receive new data. This
allows the 512-byte buffer to be written without
software intervention.
If the USB interface receives a packet which has a
length lower than the maximum packet size (writ-
ten in the CNT2RXR register, see Note below), the
USB interface switches back to normal mode and
generates a CTR interrupt and the STAT_RX bits
of the EP2R register are set to NAK by hardware
as in normal mode.
Upload Mode
OUT transactions are managed in the same way
as normal mode and IN transactions are managed
by hardware in the same way as OUT transactions
in download mode.
Bits 5:4 Reserved, forced by hardware to 0.
Bit 3 = CTR_RX
Reception Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed in reception. This bit must
be cleared after that the corresponding interrupt
has been serviced.
Bit 2 = DTOG_RX
Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
USB INTERFACE (Cont’d)
The receiver toggles DTOG_RX only if it receives
a correct data packet and the packet’s data PID
matches the receiver sequence bit.
Bits 1:0 = STAT_RX [1:0]
Status bits, for reception
transfers.
These bits contain the information about the end-
point status, which is listed below:
Table 22. Reception Status Encoding
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint, so the software has the time to examine
the received data before acknowledging a new
transaction.
Note: These bits are write protected in download
mode (if MOD[1:0] =10b in the EP2RXR register)
ENDPOINT
2
TRANSMISSION
REGISTER
(EP2TXR)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling Endpoint 2
transmission. It is also reset by a USB reset, either
received from the USB or forced through the
FRES bit in the CTLR register.
Bit 3 = CTR_TX
Transmission Transfer Correct.
This bit is set by hardware when a correct transfer
operation is performed in transmission. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR in transmission on Endpoint 2
1: Correct transfer in transmission on Endpoint 2
STAT_RX1 STAT_RX0
Meaning
00
DISABLED: reception trans-
fers cannot be executed.
01
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
10
NAK: the endpoint is naked
and all reception requests re-
sult in a NAK handshake.
11
VALID: this endpoint is ena-
bled for reception.
70
000
0
CTR_T
X
DTOG
_TX
STA T_
TX1
STAT _
TX0
1
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