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參數(shù)資料
| 型號： | ST72F652R4T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, TQFP-64 |
| 文件頁數(shù)： | 158/160頁 |
| 文件大小： | 974K |
| 代理商： | ST72F652R4T1 |
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ST7265
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.7.4.3 Slave Configuration
In slave configuration, the serial clock is received
on the SCK pin from the master device.
The value of the SPR[2:0] bits is not used for the
data transfer.
Procedure
1. For correct data transfer, the slave device
must be in the same timing mode as the
master device (CPOL and CPHA bits). See
Figure 60.
2. The SS pin must be connected to a low level
signal during the complete byte transmit
sequence or, in software mode, clear the SSI
bit in the SPICSR register.
3. Clear the MSTR bit and set the SPE bit to
assign the pins to alternate function.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPIDR register is
read, the SPI peripheral returns this buffered val-
ue.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set.
2. A write or a read of the DR register.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 11.7.4.8).
Caution: If the CPHA bit=0, use the following pro-
cedure to write to the SPIDR register between
each data byte transfer and to avoid a write colli-
sion (see Section 11.7.4.6).
1. SS must be set at high level:
By hardware:
SSM bit=0 (Hardware mode)
High level on SS pin
By software:
SSM bit = 1 (Software mode)
SSI bit = 1
2. Write the data to be transmitted in the SPIDR
register.
3. SS must be set at low level (by Hardware or in
Software mode).
Slave in Halt mode
In slave configuration, the SPI is able to exit the
ST7 device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selec-
tion is configured as external (see Section
11.7.4.1), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
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