參數(shù)資料
型號: ST72F321M
廠商: 意法半導(dǎo)體
英文描述: 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 80引腳8位微控制器32至60,000閃存/ ROM,ADC的,5個定時器,SPI和SCI的I2C接口(具有比較方案,國際檢察官聯(lián)合會,嵌套中斷,中華語文研習所,人事登記的8位微控制器)
文件頁數(shù): 42/178頁
文件大?。?/td> 3121K
代理商: ST72F321M
ST72F321M, ST72321BM
42/178
POWER SAVING MODES
(Cont’d)
8.3 WAIT MODE
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to
Figure 24
.
Figure 24. WAIT Mode Flow-chart
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
WFI
INSTRUCTION
RESET
INTERRUPT
Y
N
N
Y
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
ON
ON
OFF
10
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
ON
OFF
ON
10
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
ON
ON
ON
XX
1)
256 OR 4096 CPU CLOCK
CYCLE DELAY
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