參數(shù)資料
型號: ST72F321M
廠商: 意法半導(dǎo)體
英文描述: 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 80引腳8位微控制器32至60,000閃存/ ROM,ADC的,5個定時器,SPI和SCI的I2C接口(具有比較方案,國際檢察官聯(lián)合會,嵌套中斷,中華語文研習所,人事登記的8位微控制器)
文件頁數(shù): 125/178頁
文件大?。?/td> 3121K
代理商: ST72F321M
ST72F321M, ST72321BM
125/178
10-BIT A/D CONVERTER (ADC)
(Cont’d)
9.8.3 Functional Description
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
AIN
) is greater than V
AREF
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
If the input voltage (V
AIN
) is lower than V
SSA
(low-
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
R
AIN
is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
9.8.3.1 A/D Converter Configuration
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the I/O
ports chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the ADCCSR register:
– Select the CS[3:0] bits to assign the analog
channel to convert.
9.8.3.2 Starting the Conversion
In the ADCCSR register:
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC
automatically.
Note:
The data is not latched, so both the low and
the high data register must be read before the next
conversion is complete, so it is recommended to
disable interrupts while reading the conversion re-
sult.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRH register. This clears EOC
automatically.
9.8.3.3 Changing the conversion channel
The application can change channels during con-
version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.
9.8.4 Low Power Modes
Note:
The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
9.8.5 Interrupts
None.
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
t
STAB
(see Electrical Characteristics)
before accurate conversions can be
performed.
HALT
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