參數(shù)資料
型號: ST72F321M
廠商: 意法半導(dǎo)體
英文描述: 80-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 80引腳8位微控制器32至60,000閃存/ ROM,ADC的,5個定時器,SPI和SCI的I2C接口(具有比較方案,國際檢察官聯(lián)合會,嵌套中斷,中華語文研習(xí)所,人事登記的8位微控制器)
文件頁數(shù): 159/178頁
文件大?。?/td> 3121K
代理商: ST72F321M
ST72F321M, ST72321BM
159/178
11.11 COMMUNICATION INTERFACE CHARACTERISTICS
11.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
DD
,
f
CPU
, and T
A
unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Figure 89. SPI Slave Timing Diagram with CPHA=0
3)
Notes:
1.
Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
Symbol
Parameter
Conditions
Min
Max
f
CPU
/4
2
f
CPU
/2
4
Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master
f
CPU
=8MHz
f
CPU
/128
0.0625
MHz
Slave
f
CPU
=8MHz
0
t
r(SCK)
t
f(SCK)
t
su(SS)
t
h(SS)
t
w(SCKH)
t
w(SCKL)
t
su(MI)
t
su(SI)
t
h(MI)
t
h(SI)
t
a(SO)
t
dis(SO)
t
v(SO)
t
h(SO)
t
v(MO)
t
h(MO)
SPI clock rise and fall time
see I/O port pin description
SS setup time
SS hold time
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
120
120
100
90
100
100
100
100
0
ns
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
120
240
90
Slave (after enable edge)
0
Master (before capture edge)
0.25
0.25
t
CPU
SS
INPUT
S
I
CPHA=0
CPOL=0
MOSI
INPUT
MISO
OUTPUT
CPHA=0
CPOL=1
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
v(SO)
t
a(SO)
t
su(SI)
t
h(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
see note 2
t
su(SS)
t
h(SS)
t
dis(SO)
t
h(SO)
see
note 2
BIT1 IN
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