參數(shù)資料
型號(hào)： ST52513F3
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PDSO20
封裝： ROHS COMPLIANT, SOP-20
文件頁(yè)數(shù)： 96/136頁(yè)
文件大?。?/td> 2791K
代理商： ST52513F3
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9 INSTRUCTION SET
ST52F510/F513 supplies 107 (98 + 9 Fuzzy)
instructions that perform computations and control
the device. Computational time required for each
instruction consists of one clock pulse for each
Cycle plus 2 clock pulses for the decoding phase.
Total computation time for each instruction is
reported in Table 9.1
The ALU of ST52F510/F513 can perform
multiplication
(MULT)
and
division
(DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
Division is performed between a 16 bit dividend
and an 8 bit divider, the result and the remainder
are stored in two 8-bit registers (see Figure 2.4).
9.1 Addressing Modes
ST52F510/F513 instructions allow the following
addressing modes:
■ Inherent: this instruction type does not require
an operand because the opcode specifies all the
information necessary to carry out the
instruction. Examples: NOP, SCF.
■ Immediate: these instructions have an operand
as a source immediate value. Examples: LDRC,
ADDI.
■ Direct: the operands of these instructions are
specified with the direct addresses. The
operands can refer (according to the opcode) to
addresses belonging to the different addressing
spaces. Example: SUB, LDRE.
■ Indirect: data addresses that are required are
found in the locations specified as operands.
Both source and/or destination operands can be
addressed indirectly. The operands can refer,
(according to the opcode) to addresses
belonging to different addressing spaces.
Examples: LDRR(reg1),(reg2);
LDER mem_addr,(reg1).
■ Bit Direct: operands of these instructions directly
address the bits of the specified Register File
locations. Examples: BSET, BTEST.
9.2 Instruction Types
ST52F510/F513 supplies the following instruction
types:
■ Load Instructions
■ Arithmetic and Logic Instructions
■ Bitwise instructions
■ Jump Instructions
■ Interrupt Management Instructions
■ Control Instructions
The instructions are listed in Table 9.1
Table 9.1 Instruction Set
Load Instructions
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
BLKSET
BLKSET const
2
(*)
-
GETPG
GETPG regx
2
7
-
LDCE
LDCE confx,memy
3
8/10
-
LDCI
LDCI confx, const
3
7
-
LDCNF
LDCNF regx, conf
3
7
-
LDCR
LDCR confx, regy
3
8
-
LDER
LDER memx, regy
3
11
-
LDER
LDER (regx),(regy)
3
12
-
LDER
LDER (regx), regy
3
11
-
LDER
LDER memx,(regy)
3
12
-
LDFR
LDFR fuzzyx, regy
3
8
-
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