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參數(shù)資料
| 型號(hào)： | ST52513F3 |
| 廠(chǎng)商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PDSO20 |
| 封裝： | ROHS COMPLIANT, SOP-20 |
| 文件頁(yè)數(shù)： | 57/136頁(yè) |
| 文件大?。?/td> | 2791K |
| 代理商： | ST52513F3 |
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3.7 Configuration Registers & Option Bytes
The ST52F510/F513 Configuration Registers
bench consists of a file of 8-bit registers that allows
the configuration of all the ICU blocks.
The registers are located inside the block they
configure in order to obtain greater flexibility and
modularity in the design of new family devices. In
the Configuration Registers, each bit has a
particular use, so the logic level of each of them
must be considered.
Some special configuration data, that needs to be
load at the start-up and not further changed, are
stored in Option Bytes. These are loaded only
during the device programming phase. See Table
Option Bytes.
The Configuration Registers are readable and
writable; the addresses refer to the same register
both in read and in write. In order to access the
Configuration Register the user can work in
several
modes
by
utilizing
the
following
instructions:
■ LDCI: loads the immediate value in the
Configuration Register specified and is the most
commonly used to write configuration data.
■ LDCR:
loads
the
Configuration
Register
specified with the contents of the specified
Register File location, allowing a parametric
configuration.
■ LDCE:
loads
the
Configuration
Register
specified with the contents of the specified
Program/Data Memory location, allowing the
configuration data to be taken from a table.
■ LDCNF: loads the
Register File location
specified with the contents of the Configuration
Register indicated, allowing for the inspection of
the configuration of the device (permitting safe
run-time modifications).
In order to simplify the concept, a mnemonic name
is assigned to each register. The same name is
used in Visual FIVE development tools. The list of
the Configuration Registers is shown in Table 3.4.
3.8 Fuzzy registers
The Decision Processor for Fuzzy computation is
accessed by means of 8 dedicated registers.
These registers are used to load values in input to
the Decision Processor.
The values are loaded in the Fuzzy Register by
mean of the LDFR instruction. This instruction set
the specified Fuzzy Register (addresses from 0 to
7) with the value stored in the specified address of
the Register File.
See Chapter 8 FUZZY COMPUTATION (DP) for
further informations.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513G2 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513G3 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513K2 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513K3 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y2 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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