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參數(shù)資料
| 型號(hào)： | ST52513F3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PDSO20 |
| 封裝： | ROHS COMPLIANT, SOP-20 |
| 文件頁(yè)數(shù)： | 134/136頁(yè) |
| 文件大?。?/td> | 2791K |
| 代理商： | ST52513F3 |
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Bit 0: SB Start bit (Master Mode)
This bit is set by hardware as soon as the
Start condition is generated (following a write
START=1). An interrupt is generated if
ITE=1. It is cleared by software reading
I2C_SR1 register followed by writing the
address byte in I2C_OUT register. It is also
cleared by hardware when the interface is
disabled (PE=0).
0: No Start condition
1: Start condition generated
I2C Status Register 2 (I2C_SR2)
Input Register 8 (08h) Read only
Reset Value: 0000 0000 (00h)
Bit 7-5: Reserved.
Bit 4: AF Acknowledge failure.
This bit is set by hardware when no
acknowledge is returned. An interrupt is
generated if ITE=1. It is cleared by software
reading the I2C_SR2 register or by hardware
when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3: STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop
condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is
generated if ITE=1. It is cleared by software
reading I2C_SR2 register or by hardware
when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2: ARLO Arbitration lost.
This bit is set by hardware when the interface
loses the arbitration of the bus to another
master. An interrupt is generated if ITE=1. It
is cleared by software reading I2C_SR2
register or by hardware when the interface is
disabled (PE=0).
After an ARLO event the interface switches
back automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bit 1: BERR Bus error.
This bit is set by hardware when the interface
detects a misplaced Start or Stop condition.
An interrupt is generated if ITE=1. It is
cleared by software reading I2C_SR2
register or by hardware when the interface is
disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note: Also a polling on BUSY bit has to be done to
detect a bus error (BUSY bit cleared by hardware).
Bit 0: GCAL General Call (Slave mode).
This bit is set by hardware when a general
call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting
a Stop condition (STOPF=1) or when the
interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
14.5.3 I2C Interface Output Registers.
I2C Data Output Register (I2C_OUT)
Output Register 6 (06h) Write only
Reset Value: 0000 0000 (00h)
bit 7-0: I2CDO7-I2CDO0 Data to be transmitted.
These bits contain the byte to be transmitted in the
bus in Transmitter mode: Byte transmission start
automatically when the software writes in the
I2C_OUT register.
70
-
AF
STOPF
ARLO
BERR
GCAL
70
I2CDO7 I2CDO6 I2CDO5 I2CDO4 I2CDO3 I2CDO2 I2CDO1 I2CDO0
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