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| 型號： | ST52513F3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PDSO20 |
| 封裝： | ROHS COMPLIANT, SOP-20 |
| 文件頁數(shù)： | 40/136頁 |
| 文件大?。?/td> | 2791K |
| 代理商： | ST52513F3 |
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19 IMPORTANT NOTES
19.1 SILICON IDENTIFICATION
This document describes the limitations that apply
to ST52F510/F513 devices, silicon revision U.
This is identifiable on:
Device package, by the last letter of Trace Code
marked on device package.
On the box, by the last 3 digits of the Internal
Sales Type printed on the box label.
19.2 SILICON LIMITATIONS
19.2.1 EEPROM writing error flag.
Description
When an instruction for writing data ("lder") is
located in a write protected page, (clearly to write
data in an unprotected page of Program/Data
Memory) the writing error flag Bit 1: PRTCD Page
Protected of IAP Status Register (IAP_SR) [Input
Register 40 (028h)] is always set even if the writing
is successful.
Workaround
Once the PRTCD bit is set it is anyway possible to
verify the correct writing of a data byte reading the
target location with the instruction "ldre" and
comparing it with the data byte intended to store.
19.2.2 CPU Prescaler after RESET.
Description
The Reset caused by the Watchdog does not reset
the
CPU
Prescaler
Configuration
Register
CPL_CLK [Configuration Register 46 (02Eh)] so
the CPU continues to run with the frequency used
before the reset.
Workaround
Software workaround can be used: if the user
thinks that a Watchdog Reset is possible, he
should take care of writing the CPU Prescaler
Configuration Register as first instruction after a
WDG reset.
19.2.3 SCI synchronization in case of consecu-
tive bytes reception.
Description.
The SCI looses synchronization in data reception
when two bytes are received consecutively,
without an idle time of at least 3/16 of bit time (3
SCI CLOCK_RX cycles).
Workaround.
To avoid lost of synchronization when two
consecutive bytes are received by the SCI, an idle
time corresponding to 3 CLOCK_RX cycles must
be guaranteed between the stop bit of each byte
and the start bit of the successive byte by the
Transmitter device.
As an implementation suggestion, this can be
achieved by configuring the external Transmitter
device with 2 Stop bits and the ST5 SCI configured
as a receiver with 1 Stop bit.
19.2.4 I2C GENERAL CALL flag.
Description.
The General Call Flag, Bit0 on I2C Status
Register 2 (I2C_SR2) [Input Register 8 (08h)] is
not reset if a second Start condition occurs without
a Stop condition or if the peripheral is not disabled
setting to zero Bit5, PE Peripheral enable, on I2C
Control
Register
(I2C_CR)
[Configuration
Register 16 (010h)].
Workaround
None. The user has to guarantee that every
communication (start condition) ends with a stop
condition.
19.2.5 HALT not skipped.
Description.
When the Hardware WDT is enabled, if HALT
instruction is preceded by wdtslp instruction or if
none of wdtslp and wdtrfr instruction occurred, Halt
is not skipped.
Workaround.
The user should avoid using HALT instruction
when hardware WatchDog is used.
Part Number
Trace Code
marked on
device
Internal Sales Type on
box label
ST52F51yxxxx
“xxxxxxxxxU”
52F51yxxxx$Uz
52F51yxxxx$A3
Legend: y= 0,3; z= 3,4,5
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513G2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513G3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513K2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513K3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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