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| 型號(hào)： | ST52510F3M6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁(yè)數(shù)： | 8/136頁(yè) |
| 文件大?。?/td> | 3335K |
| 代理商： | ST52510F3M6 |
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15.5 SPI Register Description
In the following sections describe the registers
used by the SPI.
15.5.1 SPI Configuration Registers.
SPI Control Register (SPI_CR)
Configuration Register 20 (014h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1 or MODF=1 in SPI_STATUS_CR
Bit 6: SPE Serial peripheral output enable.
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 15.4.5 Master
0: I/O port connected to pins
1: SPI alternate functions connected to pins
Note: The SPE bit is cleared by reset, so the SPI
peripheral is not initially connected to the pins.
Bit 5: SPR2 Divider Enable.
This bit is set and cleared by software and it
is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4: MSTR Master/Slave mode select.
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 15.4.5 Master
0: Slave mode is selected
1: Master mode is selected, the function of
the SCK pin changes from an input to an
output and the functions of the MISO and
MOSI pins are reversed.
Bit 3: CPOL Clock polarity.
This bit is set and cleared by software. This
bit determines the steady state of the serial
Clock. The CPOL bit affects both the master
and slave modes.
0: The steady state is a low value at the SCK
pin.
1: The steady state is a high value at the SCK
pin.
Note: SPI must be disabled by resetting the SPE
bit if CPOL is changed at the communication byte
boundaries.
Bit 2: CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data
capture edge.
1: The second clock transition is the first
capture edge.
Bit 1-0: SPR1-SPR0 Serial peripheral rate.
These bits are set and cleared by software.
Used with the SPR2 bit, they select one of six
baud rates to be used as the serial clock
when the device is a master (see Table 15.1).
These 2 bits have no effect in slave mode.
Remark: It is recommended to write the SPI_CR
register after the SPI_STATUS_CR register when
working in master mode, vice versa when working
in slave mode.
1) This configuration is allowed only for master transmit, not for
master or slave receive.
SPI Control-Status Register (SPI_STATUS_CR)
Configuration Register 21 (015h) Read/Write
Reset Value: 0000 0000 (00h)
70
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Table 15.1 Serial Peripheral Baud Rate
Serial Clock
SPR2
SPR1
SPR0
fCKM/2
1)
10
0
fCKM/4
0
fCKM/8
0
1
fCKM/16
1
0
fCKM/32
0
1
0
fCKM/64
0
1
70
SPIF
WCOL
OR
MODF
-
SOD
SSM
SSI
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ST52510G2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52510G3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52510K2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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| ST52510Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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