參數(shù)資料
型號： ST52510F3M6
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PDSO20
封裝： SOP-20
文件頁數(shù)： 78/136頁
文件大?。?/td> 3335K
代理商： ST52510F3M6
Obsolete
Product(s)
- Obsolete
Product(s)
6 CLOCK, RESET & POWER SAVING MODES
6.1 Clock
The ST52F510/F513 Clock Generator module
generates the internal clock for the internal Control
Unit, ALU and on-chip peripherals. The Clock is
designed to require a minimum of external
components.
ST52F510/F513 devices supply the internal
oscillator in four clock modes:
■ External oscillator
■ External clock
■ Internal clock
The device always starts in internal clock mode,
excluding any external clock source. After the
start-up phase the clock is configured according to
the user definition programmed in the Option Byte
0 (OSC_CR). The internal clock generator can
supply an internal clock signal with a fixed
frequency of 10 MHz ± 1%, without the need for
external components. In order to obtain the
maximum accuracy, the frequency can be
calibrated by configuring the related Option byte 2
(OSC_SET).
The external oscillator mode uses a quartz crystal
or a ceramic resonator connected to OSCin and
OSCout as illustrated in Figure 6.1. This figure also
illustrates the connection of an external clock.
The ST52F510/F513 oscillator circuit generates an
internal clock signal with the same period and
phase as the OSCIN input pin. The maximum
frequency allowed is 20 MHz.
When the external oscillator is used, the loop gain
can be adapted to the various frequencies values
by configuring the three bits of the Option Byte 1
CLK_SET (see Register Description, Table 6.1).
When an external clock is used, it must be
connected to the pin OSCIN while OSCOUT can
be floating. In this case, Option Byte 1 bits must be
written with 0 (000).
The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially
Rs), oscillator load capacitance (CL), IC
parameters, environment temperature and supply
voltage.
The crystal or ceramic leads and circuit
connections must be as short as possible. Typical
values for CL1, CL2 are 10pF for a 20 MHz crystal.
Figure 6.1 illustrates the possible connections.
The clock signal generates two internal clock
signals: one for the CPU and one for the
peripherals. The CPU clock frequency can be
reduced,
in
order
to
decrease
current
consumption,
by
setting
the
CPU_CLK
Configuration Register 46 (02Eh). The CPU clock
can be reduced up to 64 times (see Register
Description).
Figure 6.1 Oscillator Connections
OSCin
OSCout
ST FIVE
OSCin
ST FIVE
OSCout
CRYSTAL CLOCK
EXTERNAL CLOCK
Cl1
10pF
Cl2
10pF
CLOCK
INPUT
相關(guān)PDF資料
PDF描述
ST52E430B/D 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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