參數(shù)資料
型號: ST52510F3M6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PDSO20
封裝: SOP-20
文件頁數(shù): 125/136頁
文件大?。?/td> 3335K
代理商: ST52510F3M6
Obsolete
Product(s)
- Obsolete
Product(s)
Acknowledge may be enabled and disabled via
software.
The I2C interface address and/or general call
address can be selected via software.
The speed of the I2C interface may be selected
between Standard (0-100KHz) and Fast I2C (100-
400KHz).
14.3.3 SDA/SCL Line Control.
Transmitter mode: the interface holds the clock line
low before transmission, in order to wait for the
microcontroller to write the byte in the Data
Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
SCL frequency is controlled by a programmable
clock divider which depends on the I2C bus mode.
When the I2C cell is enabled, the SDA and SCL
pins must be configured as open-drain with or
without pull-up. The value of the external pull-up
resistance used depends on the application.
14.4 Functional Description
By default the I2C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First, the interface frequency must be configured
using the related bits of the Configuration
Registers.
14.4.1 Slave Mode.
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Figure 14.2 I2C Interface Block Diagram
DATA REGISTER
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER (OAR)
CLOCK CONTROL REGISTER (I2C_CCR)
STATUS REGISTER 1 (I2C_SR1)
CONTROL REGISTER (I2C_CR)
SDA
SCL
CONTROL LOGIC
STATUS REGISTER 2 (I2C_SR2)
INTERRUPT
CLOCK CONTROL
DATA CONTROL
SCL
SDA
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