參數(shù)資料
型號: ST16C2550
廠商: Exar Corporation
英文描述: Dual UART with 16-Byte of Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出))
中文描述: 雙UART具有16的發(fā)送和接收FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出字節(jié)))
文件頁數(shù): 21/34頁
文件大?。?/td> 314K
代理商: ST16C2550
ST16C2550
21
Rev. 3.40
Logic 1 = The -RI input to the 2550 has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be
generated.
MSR BIT-3:
Logic 0 = No -CD Change. (normal default condition)
Logic 1 = Indicates that the -CD input to the has changed
state since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-4:
During normal operation, this bit is the compliment of
the -CTS input. During the loop-back mode this bit is
equivalent to MCR bit-1 (-RTS).
MSR BIT-5:
During normal operation, this bit is the compliment of
the -DSR input. During the loop-back mode, this bit is
equivalent to MCR bit-0 (-DTR).
MSR BIT-6:
During normal operation, this bit is the compliment of
the -RI input. Reading this bit in the loop-back mode
produces the state of MCR bit-2 (-OP1)
MSR BIT-7:
During normal operation, this bit is the compliment of
the -CD input. Reading this bit in the loop-back mode
produces the state of MCR bit-3 (-OP2).
Note: Whenever any MSR bit 0-3: is set to logic “1”, a
MODEM Status Interrupt will be generated.
Scratchpad Register (SPR)
The ST16C2550 provides a temporary data register to
store 8 bits of user information.
ST16C2550 EXTERNAL RESET CONDITION
REGISTERS
RESET STATE
IER
FCR
ISR
LCR
MCR
LSR
IER BITS 0-7=0
FCR BITS 0-7=0
ISR BIT-0=1, ISR BITS 1-7=0
LCR BITS 0-7=0
MCR BITS 0-7=0
LSR BITS 0-4=0,
LSR BITS 5-6=1 LSR, BIT 7=0
MSR BITS 0-3=0,
MSR BITS 4-7=input signals
SFR BITS 0-7=1
DLL BITS 0-7=X
DLM BITS 0-7=X
MSR
SPR
DLL
DLM
OUTPUTS
RESET STATE
TX A/B
-OP2 A/B
-RTS A/B
-DTR A/B
INT A/B
Logic 1
Logic 1
Logic 1
Logic 1
Three-state condition
相關(guān)PDF資料
PDF描述
ST16C2552 Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出))
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