- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384931 > ST16C2550 (Exar Corporation) Dual UART with 16-Byte of Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出）) PDF資料下載
參數(shù)資料
| 型號： | ST16C2550 |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 16-Byte of Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出）) |
| 中文描述： | 雙UART具有16的發(fā)送和接收FIFO（雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出字節(jié)）） |
| 文件頁數(shù)： | 16/34頁 |
| 文件大?。?/td> | 314K |
| 代理商： | ST16C2550 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
ST16C2550
16
Rev. 3.40
IER BIT-0:
In the 16C450 mode, This interrupt will be issued when
the RHR has data or is cleared when the RHR is empty.
In the FIFO mode, this interrupt will be issued when the
FIFO has reached the programmed trigger level or is
cleared when the FIFO drops below the trigger level.
Logic 0 = Disable the receiver ready (ISR level 2,
RXRDY) interrupt. (normal default condition)
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
IER BIT-1:
In the 16C450 mode, this interrupt will be issued
whenever the THR is empty and is associated with bit-
5 in the LSR register. In the FIFO modes, this interrupt
will be issued whenever the FIFO is empty.
Logic 0 = Disable the Transmit Holding Register Empty
(TXRDY) interrupt. (normal default condition)
Logic 1 = Enable the TXRDY (ISR level 3) interrupt.
IER BIT-2:
This interrupt will be issued whenever an receive data
error condition exists as reflected in LSR bits 1-4.
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
IER BIT-3:
This interrupt will be issued whenever there is a
modem status change as reflected in MSR bits 0-3.
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-7:
Not Used - initialized to a logic 0.
FIFO Control Register (FCR)
This register is used to enable the FIFO’s, clear the
FIFO’s, set the receive FIFO trigger levels, and select
the DMA mode. The DMA, and FIFO modes are
defined as follows:
DMA MODE
Mode 0
transmit or receive operation, and is similar to the
ST16C450 mode. Transmit Ready (-TXRDY) on 44/48
Set and enable the interrupt for each single
pin packages will go to a logic 0 whenever the FIFO
(THR, if FIFO is not enabled) is empty. Receive Ready
(-RXRDY) on 44,/48 pin packages will go to a logic 0
whenever the Receive Holding Register (RHR) s oaded
with a character.
Mode 1
Set and enable the interrupt in a block
mode operation. The transmit interrupt is set when the
transmit FIFO is empty. -TXRDY on 44/48 pin packages
remains a logic 0 as long as one empty FIFO location
is available. The receive interrupt is set when the receive
FIFO fills to the programmed trigger level. However the
FIFO continues to fill regardless of the programmed
level until the FIFO is full. -RXRDY on 44/48 pin pack-
ages transitions low when the FIFO reaches the trigger
level, and transitions high when the FIFO empties.
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a “1” when other FCR bits are written to or
they will not be programmed.
FCR BIT-1:
Logic 0 = Receive FIFO not reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered). This bit will return to a logic
0 after clearing the FIFO.
FCR BIT-2:
Logic 0 = Transmit FIFO not reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condition)
Logic 1 = Set DMA mode “1.”
Transmit operation in mode “0”:
When the 2550 is in the ST16C450 mode (FIFO’s
disabled, FCR bit-0 = logic 0) or in the FIFO mode
(FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-3 = logic
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C2552 | Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出）) |
| ST16C450 | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
| ST16C450CJ44 | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
| ST16C450CP40 | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
| ST16C450CQ48 | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2550_04 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO |
| ST16C2550CJ-0A-EB | 功能描述:界面開發(fā)工具 Supports C2550 44 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| ST16C2550CJ44 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO |
| ST16C2550CJ44-F | 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550CJ44TR-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。