參數(shù)資料
型號(hào): ST16C2550
廠商: Exar Corporation
英文描述: Dual UART with 16-Byte of Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出))
中文描述: 雙UART具有16的發(fā)送和接收FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出字節(jié)))
文件頁數(shù): 12/34頁
文件大?。?/td> 314K
代理商: ST16C2550
ST16C2550
12
Rev. 3.40
DMA Operation
The 2550 FIFO trigger level provides additional flexibility
to the user for block mode operation. LSR bits 5-6
provide an indication when the transmitter is empty or
has an empty location(s). The user can optionally
operate the transmit and receive FIFO’s in the DMA
mode (FCR bit-3). When the transmit and receive
FIFO’s are enabled and the DMA mode is deactivated
(DMA Mode “0”), the 2550 activates the interrupt output
pin for each data transmit or receive operation. When
DMA mode is activated (DMA Mode “1”), the user takes
the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by
the receive trigger level and the transmit FIFO. In this
mode, the 2550 sets the TXRDY( or RXRDY) output pin
when characters in the transmit FIFO is below 16, or the
characters in the receive FIFO’s are above the receive
trigger level.
Loop-back Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally (See Figure 4). MCR register bits 0-
3 are used for controlling loop-back diagnostic testing.
In the loop-back mode, the transmitter output (TX) and
the receiver input (RX) are disconnected from their
associated interface pins, and instead are connected
together internally . The -CTS, -DSR, -CD, and -RI are
disconnected from their normal modem control inputs
pins, and instead are connected internally to -RTS, -
DTR, MCR bit-3 (-OP2) and MCR bit-2 (-OP1). Loop-
back test data is entered into the transmit holding
register via the user data bus interface, D0-D7. The
transmit UART serializes the data and passes the serial
data to the receive UART via the internal loop-back
connection. The receive UART converts the serial data
back into parallel data that is then made available at the
user data interface, D0-D7. The user optionally com-
pares the received data to the initial transmitted data for
verifying error free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are
fully operational. The Modem Control Interrupts are also
operational.
相關(guān)PDF資料
PDF描述
ST16C2552 Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出))
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