參數(shù)資料
型號(hào): ST16C2550
廠商: Exar Corporation
英文描述: Dual UART with 16-Byte of Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出))
中文描述: 雙UART具有16的發(fā)送和接收FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出字節(jié)))
文件頁數(shù): 17/34頁
文件大小: 314K
代理商: ST16C2550
ST16C2550
17
Rev. 3.40
0) and when there are no characters in the transmit FIFO
or transmit holding register, the -TXRDY pin in 44/48 pin
packages will be a logic 0. Once active the -TXRDY pin
will go to a logic 1 after the first character is loaded into
the transmit holding register.
Receive operation in mode “0”:
When the 2550 is in mode “0” (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin on 44/48 pin packages will go to
a logic 1 when there are no more characters in the
receiver.
Transmit operation in mode “1”:
When the 2550 is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the -TXRDY pin on 44/48 pin
packages will be a logic 1 when the transmit FIFO is
completely full. It will be a logic 0 if one or more FIFO
locations are empty.
Receive operation in mode “1”:
When the 2550 is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin on 44/48 pin packages will go to a logic 0.
Once activated, it will go to a logic 1 after there are no
more characters in the FIFO.
FCR BIT 4-5:
Not Used - initialized to a logic 0.
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level = 1)
These bits are used to set the trigger level for the
receive FIFO interrupt.
An interrupt is generated when the number of charac-
ters in the FIFO equals the programmed trigger level.
However the FIFO will continue to be loaded until it is
full.
BIT-7
BIT-6
RX FIFO trigger level
0
0
1
1
0
1
0
1
01
04
08
14
Interrupt Status Register (ISR)
The 2550 provides four levels of prioritized interrupts
to minimize external software interaction. The Inter-
rupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR
will provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. A lower
level interrupt may be seen after servicing the higher
level interrupt and rereading the interrupt status bits.
The Interrupt Source Table 6 (below) shows the data
values (bits 0-3) for the four prioritized interrupt levels
and the interrupt sources associated with each of these
interrupt levels:
相關(guān)PDF資料
PDF描述
ST16C2552 Dual UART with 16-Byte Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器(帶16字節(jié)接收和發(fā)送先進(jìn)先出))
ST16C450 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
ST16C450CJ44 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
ST16C450CP40 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
ST16C450CQ48 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
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