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| 型號： | ST16C2550 |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 16-Byte of Transmit and Receive FIFO(雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出）) |
| 中文描述： | 雙UART具有16的發(fā)送和接收FIFO（雙通用異步接收器/發(fā)送器（帶16字節(jié)接收和發(fā)送先進先出字節(jié)）） |
| 文件頁數(shù)： | 15/34頁 |
| 文件大?。?/td> | 314K |
| 代理商： | ST16C2550 |
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ST16C2550
15
Rev. 3.40
Transmit (THR) and Receive (RHR) Holding Regis-
ters
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift Reg-
ister (TSR). The status of the THR is provided in the Line
Status Register (LSR). Writing to the THR transfers the
contents of the data bus (D7-D0) to the TSR and UART
via the THR, providing that the THR is empty. The THR
empty flag in the LSR register will be set to a logic 1 when
the transmitter is empty or when data is transferred to
the TSR. Note that a write operation can be performed
when the THR empty flag is set (logic 0 = at least one
byte in FIFO/THR, logic 1= FIFO/THR empty).
The serial receive section also contains an 8-bit Receive
Holding Register, RHR and a Receive Serial Shift
Register (RSR). Receive data is removed from the 2550
and receive FIFO by reading the RHR register. The
receive section provides a mechanism to prevent false
starts. On the falling edge of a start or false start bit, an
internal receiver counter starts counting clocks at the
16x clock rate. After 7 1/2 clocks the start bit time should
be shifted to the center of the start bit. At this time the
start bit is sampled and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the
receiver from assembling a false character. Receiver
status codes will be posted in the LSR.
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line
status and modem status registers. These interrupts
would normally be seen on the INT A-B output pins.
IER Vs Transmit/Receive FIFO Interrupt Mode
Operation
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the receive interrupts and register status will reflect
the following:
A) The receive RXRDY interrupt (Level 2 ISR inter-
rupt) is issued to the external CPU when the receive
FIFO has reached the programmed trigger level. It will
be cleared when the receive FIFO drops below the
programmed trigger level.
B) Receive FIFO status will also be reflected in the
user accessible ISR register when the receive FIFO
trigger level is reached. Both the ISR register receive
status bit and the interrupt will be cleared when the
FIFO drops below the trigger level.
C) The receive data ready bit (LSR BIT-0) is set as
soon as a character is transferred from the shift
register (RSR) to the receive FIFO. It is reset when the
FIFO is empty.
D) When the Transmit FIFO and interrupts are en-
abled, an interrupt is generated when the transmit
FIFO is empty due to the unloading of the data by the
TSR and UART for transmission via the transmission
media. The interrupt is cleared either by reading the
ISR register or by loading the THR with new data
characters.
IER Vs Receive/Transmit FIFO Polled Mode Op-
eration
When FCR BIT-0 equals a logic 1; resetting IER bits
0-3 enables the 2550 in the FIFO polled mode of
operation. In this mode interrupts are not generated
and the user must poll the LSR register for TX and/or
RX data status. Since the receiver and transmitter
have separate bits in the LSR either or both can be
used in the polled mode by selecting respective
transmit or receive control bit(s).
A) LSR BIT-0 will be a logic 1 as long as there is one
byte in the receive FIFO.
B) LSR BIT 1-4 will provide the type of receive errors,
or a receive break, if encountered.
C) LSR BIT-5 will indicate when the transmit FIFO is
empty.
D) LSR BIT-6 will indicate when both the transmit
FIFO and transmit shift register are empty.
E) LSR BIT-7 will show if any FIFO data errors occurred.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2550_04 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO |
| ST16C2550CJ-0A-EB | 功能描述:界面開發(fā)工具 Supports C2550 44 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| ST16C2550CJ44 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUART WITH 16-BYTE FIFO |
| ST16C2550CJ44-F | 功能描述:UART 接口集成電路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550CJ44TR-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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