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參數(shù)資料
| 型號： | ST16654 |
| 廠商： | Exar Corporation |
| 英文描述： | QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER |
| 中文描述： | 四UART的64字節(jié)FIFO和紅外線（IrDA）編碼/解碼器 |
| 文件頁數(shù)： | 6/49頁 |
| 文件大?。?/td> | 444K |
| 代理商： | ST16654 |
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ST16C654/654D
5-70
Rev. 4.10
SYMBOL DESCRIPTION
UARTs (A-D) are enabled when the -CS pin is a logic 0. An
individual UART channel is selected by the data contents of
address bits A3-A4. When the 16 mode is selected (68/100
pin devices), this pin functions as -CSA, see definition under
-CS A-B. This pin is not available on 64 pin packages which
operate in the 16 mode only.
-CS A-B
-CS C-D
16,20
50,54
13,17
64,68
7,11
38,42
I
Chip Select A, B, C, D (active low) - This function is
associated with the 16 mode only, and for individual chan-
nels, “A” through “D.” When in 16 Mode, these pins enable
data transfers between the user CPU and the ST16C654 for
the channel(s) addressed. Individual UART sections (A, B,
C, D) are addressed by providing a logic 0 on the respective
-CS A-D pin. When the 68 mode is selected, the functions
of these pins are reassigned. 68 mode functions are de-
scribed under the their respective name/pin headings.
-CSRDY
-
76
-
I
Control Status Ready (active low) - This feature is available
on 100 pin QFP packages only. On 100 pin packages, the
Contents of the FIFORDY Register is read when this pin is
a logic 0. However it should be noted, D0-D3 will contain the
inverted logic states of TXRDY, status bits A-D, and D4-D7
the inverted logic states of RXRDY, status bits D4-D7.
D0-D2
D3-D7
66-68
1-5
88-90
91-95
53-55
56-60
I/O
Data Bus (Bi-directional) - These pins are the eight bit, three
state data bus for transferring information to or from the
controlling CPU. D0 is the least significant bit and the first
data bit in a transmit or receive serial data stream.
GND
GND
6,23
40,57
96,20
46,71
14,28
45,61
Pwr
Signal and power ground.
INT A-B
INT C-D
15,21
49,55
12,18
63,69
6,12
37,43
O
Interrupt A, B, C, D (active high) - This function is associated
with the 16 mode only. These pins provide individual
channel interrupts, INT A-D. INT A-D are enabled when
MCR bit-3 is set to a logic 1, interrupts are enabled in the
interrupt enable register (IER), and when an interrupt con-
Symbol
Pin
100
Signal
type
Pin Description
68
64
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| ST16C1450_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART |
| ST16C1450CJ28 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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