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參數(shù)資料
| 型號： | ST16654 |
| 廠商： | Exar Corporation |
| 英文描述： | QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER |
| 中文描述： | 四UART的64字節(jié)FIFO和紅外線（IrDA）編碼/解碼器 |
| 文件頁數(shù)： | 13/49頁 |
| 文件大?。?/td> | 444K |
| 代理商： | ST16654 |
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ST16C654/654D
5-77
Rev. 4.10
GENERAL DESCRIPTION
The 654 provides serial asynchronous receive data
synchronization, parallel-to-serial and serial-to-paral-
lel data conversions for both the transmitter and
receiver sections. These functions are necessary for
converting the serial data stream into parallel data that
is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding
start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integ-
rity is insured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for
any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially
when manufactured on a single integrated silicon
chip. The ST16C654 represents such an integration
with greatly enhanced features. The 654 is fabricated
with an advanced CMOS process to achieve low drain
power and high speed requirements.
The 654 is an upward solution that provides 64 bytes
of transmit and receive FIFO memory, instead of 16
bytes provided in the 16/68C554, or none in the 16/
68C454. The 654 is designed to work with high speed
modems and shared network environments, that re-
quire fast data processing time. Increased perfor-
mance is realized in the 654 by the larger transmit and
receive FIFOs. This allows the external processor to
handle more networking tasks within a given time. For
example, the ST16C554 with a 16 byte FIFO, unloads
16 bytes of receive data in 1.53 ms (This example
uses a character length of 11 bits, including start/stop
bits at 115.2Kbps). This means the external CPU will
have to service the receive FIFO at 1.53 ms intervals.
However with the 64 byte FIFO in the 654, the data
buffer will not require unloading/loading for 6.1 ms.
This increases the service interval giving the external
CPU additional time for other applications and reduc-
ing the overall UART interrupt servicing time. In
addition, the 4 selectable levels of FIFO trigger inter-
rupt and automatic hardware/software flow control is
uniquely provided for maximum data throughput per-
formance especially when operating in a multi-chan-
nel environment. The combination of the above
greatly reduces the bandwidth requirement of the
external controlling CPU, increases performance, and
reduces power consumption.
The 654 combines the package interface modes of the
16C454/554 and 68/C454/554 series on a single inte-
grated chip. The 16 mode interface is designed to
operate with the Intel type of microprocessor bus while
the 68 mode is intended to operate with Motorola, and
other popular microprocessors. Following a reset, the
654 is down-ward compatible with the ST16C454/
ST68C454 or the ST68C454/ST68C554 dependent
on the state of the interface mode selection pin, 16/-
68.
The 654 is capable of operation to 1.5Mbps with a 24
MHz crystal or external clock input.
With a crystal of 14.7464 MHz and through a software
option, the user can select data rates up to 460.8Kbps
or 921.6Kbps, 8 times faster than the 16C554.
The rich feature set of the 654 is available through
internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger
levels, selectable TX and RX baud rates, infrared
encoder/decoder interface, modem interface con-
trols, and a sleep mode are all standard features. MCR
bit-5 provides a facility for turning off (Xon) software
flow control with any incoming (RX) character. In the
16 mode INTSEL and MCR bit-3 can be configured to
provide a software controlled or continuous interrupt
capability. Due of pin limitations for the 64 pin 654 this
feature is offered by two different QFP packages. The
ST16C654DCQ64 operates in the continuos interrupt
enable mode by bonded INTSEL to VCC internally.
The ST16C654CQ64 operates in conjunction with
MCR bit-3 by bonding INTSEL to GND internally.
The 68 and 100 pin ST16C654 packages offer a clock
select pin to allow system/board designers to preset
the default baud rate table. The CLKSEL pin selects
the 1X or 4X pre-scaleable baud rate generator table
during initialization, but can be overridden following
initialization by MCR bit-7.
The 100 pin packages offer several enhances fea-
tures. These features include an MIDI clock input, an
internal FIFO monitor register, and separate IrDA TX
outputs. The MIDI (Musical Instrument Digital Inter-
face) can be connected to the XTAL2 pin for normal
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