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參數(shù)資料
| 型號： | ST16654 |
| 廠商： | Exar Corporation |
| 英文描述： | QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER |
| 中文描述： | 四UART的64字節(jié)FIFO和紅外線（IrDA）編碼/解碼器 |
| 文件頁數(shù)： | 14/49頁 |
| 文件大?。?/td> | 444K |
| 代理商： | ST16654 |
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ST16C654/654D
5-78
Rev. 4.10
operation or to external MIDI oscillator for MIDI appli-
cations. A separate register is provided for monitoring
the realtime status of the FIFO signals -TXRDY and -
RXRDY for each of the four UART channels (A-D).
This reduces polling time involved in accessing indi-
vidual channels. The 100 pin QFP package also
offers, four separate IrDA (Infrared Data Association
Standard) outputs for Infrared applications. These
outputs are provided in addition to the standard asyn-
chronous modem data outputs.
FUNCTIONAL DESCRIPTIONS
Interface Options
Two user interface modes are selectable for the 654
package. These interface modes are designated as
the “16 mode” and the “68 mode.” This nomenclature
corresponds to the early 16C454/554 and 68C454/
554 package interfaces respectively.
The 16 Mode Interface
The 16 mode configures the package interface pins for
connection as a standard 16 series (Intel) device and
operates similar to the standard CPU interface avail-
able on the 16C454/554. In the 16 mode (pin 16/-68
logic 1) each UART is selected with individual chip
select (CSx) pins as shown in Table 2 below.
Table 2, SERIAL PORT CHANNEL SELECTION
GUIDE, 16 MODE INTERFACE
-CSA
-CSB
-CSC
-CSD
UART
CHANNEL
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
None
A
B
C
D
The 68 Mode Interface
The 68 mode configures the package interface pins for
connection with Motorola, and other popular micro-
processor bus types. The interface operates similar to
the 68C454/554. In this mode the 654 decodes two
additional addresses, A3-A4 to select one of the four
UART ports. The A3-A4 address decode function is
used only when in the 68 mode (16/-68 logic 0), and is
shown in Table 3 below.
Table 3, SERIAL PORT CHANNEL SELECTION
GUIDE, 68 MODE INTERFACE
-CS
A4
A3
UART
CHANNEL
1
0
0
0
0
N/A
0
0
1
1
N/A
0
1
0
1
None
A
B
C
D
Internal Registers
The 654 provides 15 (64/68 pin packages) or 16 (100
pin packages) internal registers for monitoring and
control. These resisters are shown in Table 4 below.
Twelve registers are similar to those already available
in the standard 16C554. These registers function as
data holding registers (THR/RHR), interrupt status
and control registers (IER/ISR), a FIFO control regis-
ter (FCR), line status and control registers (LCR/LSR),
modem status and control registers (MCR/MSR), pro-
grammable data rate (clock) control registers (DLL/
DLM), and a user assessable scratchpad register
(SPR). Beyond the general 16C554 features and
capabilities, the 654 offers an enhanced feature reg-
ister set (EFR, Xon/Xoff 1-2) that provides on board
hardware/software flow control. Register functions
are more fully described in the following paragraphs.
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