參數(shù)資料
型號: ST16654
廠商: Exar Corporation
英文描述: QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER
中文描述: 四UART的64字節(jié)FIFO和紅外線(IrDA)編碼/解碼器
文件頁數(shù): 33/49頁
文件大?。?/td> 444K
代理商: ST16654
ST16C654/654D
5-97
Rev. 4.10
hardware flow control is disabled.
0 = Automatic RTS flow control is disabled. (normal
default condition)
1 = Enable Automatic RTS flow control.
EFR bit-7:
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled.
(normal default condition)
Logic 1 = Enable Automatic CTS flow control. Trans-
mission will stop when -CTS goes to a logical 1.
Transmission will resume when the -CTS pin returns
to a logical 0.
FIFO READY REGISTER
This register is applicable to 100 pin ST16C654s only.
The FIFO resister provides the realtime status of the
transmit and receive FIFOs. Each TX and RX cannel
(A-D) has its own 64 byte FIFO. When any of the eight
TX/RX FIFOs become full, a bit associated with its TX/
RX function and channel A-D is set in the FIFO status
register.
FIFO channel A-D RDY Bit 0-3:
0 = The transmit FIFO A-D associated with this bit is
full. This channel will not accept any more transmit
data.
1 = One or more empty locations exist in the FIFO.
FIFORdy Bit 4-7:
0 = The receive FIFO is above the programmed
trigger level or time-out is occurred.
1 = Receiver is ready and is below the programmed
trigger level.
ST16C654 EXTERNAL RESET CONDITIONS
REGISTERS
RESET STATE
IER
ISR
LCR
MCR
LSR
IER BITS 0-7=0
ISR BIT-0=1, ISR BITS 1-7=0
LCR BITS 0-7=0
MCR BITS 0-7=0
LSR BITS 0-4=0,
LSR BITS 5-6=1 LSR, BIT 7=0
MSR BITS 0-3=0,
MSR BITS 4-7= input signals
FCR BITS 0-7=0
EFR BITS 0-7=0
MSR
FCR
EFR
SIGNALS
RESET STATE
TX A-D
-RTS A-D
-DTR A-D
-RXRDY A-D
-TXRDY A-D
High
High
High
High
Low
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