
Memory organization
ST10F296E
When CAN1, CAN2, RTC, ASC1, SSC1, I2C, PWM1, XBus additional features, XTimer and
XPort modules are disabled via XPERCON settings, any access in the address range
00’E800h to 00’EFFFh is directed to the external memory interface, using the BUSCONx
register associated with the ADDRSELx register matching the target address. All pins
involved with the XPeripherals can be used as general purpose IOs whenever the related
module is not enabled.
The default XPER selection after reset is identical to configuration of the XBus in the
ST10F280. CAN1 and XRAM1 are enabled, CAN2 and XRAM2 are disabled, all other
XPeripherals are disabled after reset.
the XPERCON register cannot be changed after globally enabling the XPeripherals (after
setting the XPEN bit in the SYSCON register).
5
XFLASHEN
XFlash enable bit
0: Access to the on-chip XFlash is disabled, external access is
performed. Address range 09’0000h to 0E’FFFFh is directed to the
external memory only if XRAM2EN is also 0.
1: The on-chip XFlash is enabled and can be accessed.
4XRTCEN
RTC enable
0: Access to the on-chip RTC module is disabled, external access is
performed. Address range 00’ED00h to 00’EDFF is directed to the
external memory only if CAN1EN, CAN2EN, XASCEN, XSSCEN,
XI2CEN, XPWMEN, XMISCEN and XPORTEN are also 0.
1: The on-chip RTC module is enabled and can be accessed.
3XRAM2EN
XRAM2 enable bit
0: Access to the on-chip 64 KByte XRAM is disabled, external access is
performed. Address range 0F’0000h to 0F’FFFFh is directed to the
external memory only if XFLASHEN is also 0.
1: The on-chip 64 Kbyte XRAM is enabled and can be accessed.
2XRAM1EN
XRAM1 enable bit
0: Access to the on-chip 2 KByte XRAM is disabled. Address range
00’E000h to 00’E7FFh is directed to the external memory.
1: The on-chip 2 Kbyte XRAM is enabled and can be accessed.
1CAN2EN
CAN2 enable bit
0: Access to the on-chip CAN2 XPeripheral and its functions is disabled
(P4.4 and P4.7 pins can be used as general purpose IOs, but, address
range 00’EC00h to 00’EFFFh is directed to the external memory only if
CAN1EN, XRTCEN, XASCEN, XSSCEN, XI2CEN, XPWMEN,
XMISCEN and XPORTEN are also 0).
1: The on-chip CAN2 XPeripheral is enabled and can be accessed.
0CAN1EN
CAN1 enable bit
0: Access to the on-chip CAN1 XPeripheral and its functions is disabled
(P4.5 and P4.6 pins can be used as general purpose IOs, but, address
range 00’EC00h to 00’EFFFh is directed to the external memory only if
CAN2EN, XRTCEN, XASCEN, XSSCEN, XI2CEN, XPWMEN an
XMISCEN are also 0).
1: The on-chip CAN1 XPeripheral is enabled and can be accessed.
Table 5.
XPERCON register description
BIt
Bit name
Function