參數(shù)資料
型號(hào): SSTUB32864EC/G
廠商: NXP SEMICONDUCTORS
元件分類: 鎖存器
英文描述: 32864 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封裝: 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96
文件頁(yè)數(shù): 3/19頁(yè)
文件大?。?/td> 113K
代理商: SSTUB32864EC/G
SSTUB32864_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
11 of 19
NXP Semiconductors
SSTUB32864
1.8 V congurable registered buffer for DDR2-800 RDIMM applications
11. Test information
11.1 Test circuit
All input pulses are supplied by generators having the following characteristics:
PRR
≤ 10 MHz; Z
0 =50 ; input slew rate = 1 V/ns ± 20 %, unless otherwise specied.
The outputs are measured one at a time with one transition per measurement.
(1) CL includes probe and jig capacitance.
Fig 6.
Load circuit
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 7.
Voltage and current waveforms; inputs active and inactive times
VID = 600 mV.
VIH =Vref + 250 mV (AC voltage levels) for differential inputs. VIH =VDD for LVCMOS inputs.
VIL =Vref 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 8.
Voltage waveforms; pulse duration
RL = 100
RL = 1000
VDD
50
CK inputs
CK
OUT
DUT
test point
002aaa371
test point
delay = 350 ps
Zo = 50
RL = 1000
CL = 30 pF(1)
LVCMOS
RESET
10 %
IDD(1)
tINACT
VDD
0.5VDD
tACT
90 %
0 V
002aaa372
0.5VDD
VICR
VIH
VIL
input
tW
VID
002aaa373
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