參數(shù)資料
型號(hào)： SPC5200CVR400
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 11/80頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT 400MHZ 272-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MPC52xx
處理器類型： 32-位 MPC52xx PowerPC
速度： 400MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 托盤
Electrical and Thermal Characteristics
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
19
Notes:
1) The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200 User Manual [1].
2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external
interrupt sources. Take care of interrupt prioritization which may increase the latencies.
Since all external interrupt signals are synchronized into the internal processor bus clock domain, each of
these signals has to exceed a minimum pulse width of more than one IP_CLK cycle.
NOTES:
1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200 User Manual
[1] for further information.
2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second
interrupt will not be recognized at all.
Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its
associated interrupt service routine also depends on the following conditions: To get a minimum interrupt
service response time, it is recommended to enable the instruction cache and set up the maximum core
clock, XL bus, and IP bus frequencies (depending on board design and programming). In addition, it is
advisable to execute an interrupt handler, which has been implemented in assembly code.
Standard GPIO Interrupts
GPIO_PSC3_4
12
IP_CLK
normal (int)
A4.7
GPIO_PSC3_5
12
IP_CLK
normal (int)
A4.8
GPIO_PSC3_8
12
IP_CLK
normal (int)
A4.9
GPIO_USB_9
12
IP_CLK
normal (int)
A4.10
GPIO_ETHI_4
12
IP_CLK
normal (int)
A4.11
GPIO_ETHI_5
12
IP_CLK
normal (int)
A4.12
GPIO_ETHI_6
12
IP_CLK
normal (int)
A4.13
GPIO_ETHI_7
12
IP_CLK
normal (int)
A4.14
GPIO WakeUp Interrupts
GPIO_PSC1_4
12
IP_CLK
normal (int)
A4.15
GPIO_PSC2_4
12
IP_CLK
normal (int)
A4.16
GPIO_PSC3_9
12
IP_CLK
normal (int)
A4.17
GPIO_ETHI_8
12
IP_CLK
normal (int)
A4.18
GPIO_IRDA_0
12
IP_CLK
normal (int)
A4.19
DGP_IN0
12
IP_CLK
normal (int)
A4.20
DGP_IN1
12
IP_CLK
normal (int)
A4.21
Table 17. Minimum pulse width for external interrupts to be recognized
Name
Min Pulse Width
Max Pulse Width
Reference Clock
SpecID
All external interrupts (IRQs, GPIOs)
> 1 clock cycle
—
IP_CLK
A4.22
Table 16. External interrupt latencies (continued)
Interrupt Type
Pin Name
Clock Cycles
Reference Clock
Core Interrupt
SpecID
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