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參數(shù)資料
| 型號： | SN54LVT8996JT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 39/41頁 |
| 文件大?。?/td> | 603K |
| 代理商： | SN54LVT8996JT |
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SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686A – APRIL 1997 – REVISED DECEMBER 1999
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
architecture
Conceptually, the ASP can be viewed as a bank of switches that can connect or isolate a module-level TAP
to/from a higher-level (e.g., module-to-module) TAP. This is shown in Figure 2. The state of the switches (open
versus closed) is based on shadow protocols, which are received on PTDI and are synchronous to PTCK.
The simple architecture of the ASP allows the system designer to overcome the limitations of IEEE Std 1149.1
ring and star configurations. Ring configurations (in which each module’s TDO is chained to the next module’s
TDI) are of limited use in backplane environments, since removal of a module breaks the scan chain and
prevents test of the remainder of the system. Star configurations (in which all module TDOs and TDIs are
connected in parallel) are suited to the backplane environment, but, since each module must receive its own
TMS, are costly in terms of backplane routing channels. By comparison, use of the ASP allows all five IEEE
Std 1149.1 signals to be routed in multidrop fashion.
1
0
Control
CON
STDI
STCK
STMS
STDO
STRST
PTDO
PTCK
PTMS
PTDI
PTRST
BYP
A9–A0
From Multidrop,
Module-to-Module
Test Access Port
To Module-Level
Test Access Port
Figure 2. ASP Conceptual Model
As shown in the functional block diagram, the ASP comprises three major logic blocks. Blocks for
shadow-protocol receive and shadow-protocol transmit are responsible for receipt of select protocol and
transmission of acknowledge protocol, respectively. The connect-control block is responsible for TAP-state
monitor and address matching.
Some additional logic is illustrated outside of these major blocks. This additional logic is responsible for
controlling the activity of the ASP outputs based on the shadow-protocol result and/or protocol bypass [as
selected by an active (low) BYP input].
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