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| 型號(hào)： | SN54LVT8996JT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 38/41頁 |
| 文件大?。?/td> | 603K |
| 代理商： | SN54LVT8996JT |
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SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686A – APRIL 1997 – REVISED DECEMBER 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
application information
In application, the ASP is used at each of several (serially-chained) groups of IEEE Std 1149.1-compliant
devices. The ASP for each such group is assigned an address (via inputs A9–A0) that is unique from that
assigned to ASPs for the remaining groups. Each ASP is wired at its primary TAP to common (multidrop) TAP
signals (sourced from a central IEEE Std 1149.1 bus master) and fans out its secondary TAP signals to the
specific group of IEEE Std 1149.1-compliant devices with which it is associated. An example is shown in
Figure 1.
ASP
IEEE Std 1149.1-
Compliant
Device Chain
PTRST
PTDI
PTMS
PTCK
PTDO
STRST
STDO
STMS
STCK
STDI
ADDR1
A9–A0
ASP
IEEE Std 1149.1-
Compliant
Device Chain
PTRST
PTDI
PTMS
PTCK
PTDO
STRST
STDO
STMS
STCK
STDI
ADDR2
A9–A0
ASP
IEEE Std 1149.1-
Compliant
Device Chain
PTRST
PTDI
PTMS
PTCK
PTDO
STRST
STDO
STMS
STCK
STDI
ADDR3
A9–A0
TRST
TDO
TMS
TCK
TDI
IEEE
Std
1149.1
Bus
Master
To
Other
Modules
BYP
Figure 1. ASP Application
This application allows the ASP to be wired to a 4- or 5-wire multidrop test access bus, such as might be found
on a backplane. Each ASP would then be located on a module, for example a printed-circuit board (PCB), that
contains a serial chain of IEEE Std 1149.1-compliant devices and that would plug into the module-to-module
bus (e.g., backplane). In the complete system, the ASP shadow protocols would allow the selection of the scan
chain on a single module. The selected scan chain could then be controlled, via the multidrop TAP, as if it were
the only scan chain in the system. Normal IR and DR scans can then be performed to accomplish the module
test objectives.
Once scan operations to a given module are complete, another module can be selected in the same fashion,
at which time the ASP-based connection to the first module is dissolved. This procedure can be continued
progressively for each module to be tested. Finally, one of two global addresses can be issued to either leave
all modules unselected (disconnect address, DSA) or to deselect and reset scan chains for all modules (reset
address, RSA).
Additionally, in Pause-DR and Pause-IR TAP states, a third global address (test-synchronization address, TSA)
can be invoked to allow simultaneous TAP-state changes and multicast scan-in operations to selected modules.
This is especially useful in the former case, for allowing selected modules to be moved simultaneously to the
Run-Test-Idle TAP state for module-level or module-to-module built-in self-test (BIST) functions, which operate
synchronously to TCK in that TAP state, and in the latter case, for scanning common test setup/data into multiple
like modules.
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