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參數(shù)資料
| 型號(hào)： | SN54LVT8996JT |
| 廠(chǎng)商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁(yè)數(shù)： | 32/41頁(yè) |
| 文件大?。?/td> | 603K |
| 代理商： | SN54LVT8996JT |
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SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686A – APRIL 1997 – REVISED DECEMBER 1999
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 24)
SN74LVT8996
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
fmax
PTCK
25
20
MHz
tPLH
BYP
↑
CON
1
8.2
1
9.4
ns
tPHL
BYP
↓
CON
1
9.8
1
11.4
ns
tPLH
BYP
↓
STMS
2.5
12
2.5
14.7
ns
tPHL
BYP
↓
STMS
2.5
11.7
2.5
13.4
ns
tPLH
PTCK
STCK
1
9.6
1
11.2
ns
tPHL
PTCK
STCK
1
10
1
11.8
ns
tPLH
PTCK
↓
CON
3.5
20.6
3.5
24.8
ns
tPHL
PTCK
↓
CON
3.5
23
3.5
27.4
ns
tPLH
PTCK
↓
PTDO
3
14.7
3
17.4
ns
tPHL
(shadow-protocol acknowledge)
PTDO
3
15
3
17.7
ns
tPLH
PTCK
↓
STMS
5.5
19.9
5.5
23.9
ns
tPHL
(connect)
STMS
5.5
19.1
5.5
22.9
ns
tPLH
PTDI
STDO
1
8.3
1
9.9
ns
tPHL
PTDI
STDO
1
8.6
1
10.2
ns
tPLH
PTMS
STMS
1
8.5
1
9.8
ns
tPHL
PTMS
STMS
1
8.8
1
10.3
ns
tPLH
PTRST
STRST
1
8.4
1
10
ns
tPHL
PTRST
STRST
1
9
1
10.5
ns
tPLH
PTRST
↓
CON
3.5
23.9
3.5
29
ns
tPLH
PTRST
↓
STMS
2.5
13.2
2.5
15.7
ns
tPLH
STDI
PTDO
1
6.8
1
8.2
ns
tPHL
STDI
PTDO
1
7.6
1
9
ns
The transitions at STMS are possible only when a shadow-protocol select is issued while STMS is held (in the OFF status) at a level that differs
from that at PTMS. Such operation is not recommended since state synchronization of the primary TAP to secondary TAP cannot be ensured.
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