參數(shù)資料
型號: SN54LVT8996JT
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24
封裝: CERAMIC, DIP-24
文件頁數(shù): 29/41頁
文件大?。?/td> 603K
代理商: SN54LVT8996JT
SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686A – APRIL 1997 – REVISED DECEMBER 1999
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 24)
SN54LVT8996
SN74LVT8996
UNIT
MIN
MAX
MIN
MAX
UNIT
f lk
Clock frequency
PTCK
VCC = 2.7 V
20
MHz
fclock
Clock frequency
PTCK
VCC = 3.3 V ± 0.3V
25
MHz
BYP low
8
t
Pulse duration
PTCK high
20
ns
tw
Pulse duration
PTCK low
12
ns
PTRST low
9
A9–A0 before PTCK
10.2
t
Setup time
PTDI before PTCK
10.1
ns
tsu
Setup time
PTMS before BYP
4
ns
PTMS before PTCK
10
A9–A0 after PTCK
4
th
Hold time
PTDI after PTCK
4
ns
th
Hold time
PTMS after BYP
4
ns
PTMS after PTCK
4
In normal application of the ASP, such timing requirements with respect to BYP are met implicitly and, therefore, need not be considered.
These requirements apply only in the case in which the address inputs are changed during a shadow protocol. For normal application of the ASP,
it is recommended that the address inputs remain static throughout any shadow protocols. In such cases, the timing of address inputs relative
to PTCK need not be considered.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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