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參數(shù)資料
| 型號： | SN54LVT8996JT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 31/41頁 |
| 文件大?。?/td> | 603K |
| 代理商： | SN54LVT8996JT |
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SN54LVT8996, SN74LVT8996
3.3-V 10-BIT ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS686A – APRIL 1997 – REVISED DECEMBER 1999
37
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued) (see Figure 24)
SN54LVT8996
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
tPZH
BYP
↓
PTDO
1.5
9.5
1.5
11.6
ns
tPZL
BYP
↓
PTDO
1.5
10.7
1.5
12.7
ns
tPZH
BYP
↓
STDO
1.5
8.6
1.5
10.2
ns
tPZL
BYP
↓
STDO
1.5
9.7
1.5
11.5
ns
tPZH
PTCK
↓
PTDO
4
15.3
4
18.2
ns
tPZH
PTCK
↓
STDO
4
16.6
4
19.6
ns
tPZL
PTCK
↓
STDO
4
17.3
4
20.5
ns
tPHZ
BYP
↑
PTDO
1.5
8.6
1.5
10.3
ns
tPLZ
BYP
↑
PTDO
1.5
8.2
1.5
7
ns
tPHZ
BYP
↑
STDO
1.5
7.6
10.4
ns
tPLZ
BYP
↑
STDO
1.5
7.4
1.5
7.9
ns
tPHZ
PTCK
↓
PTDO
3
15
3
18.1
ns
tPLZ
PTCK
↓
PTDO
3
14.4
3
16.3
ns
tPHZ
PTCK
↓
STDO
3.5
16.9
3.5
18.8
ns
tPLZ§
PTCK
↓
STDO
3.5
13.8
3.5
16.7
ns
tPHZ
PTRST
↓
PTDO
3.5
19.6
3.5
26.2
ns
tPLZ
PTRST
↓
PTDO
3.5
19.3
3.5
21.3
ns
tPHZ
PTRST
↓
STDO
4.5
19.4
4.5
23.6
ns
tPLZ
PTRST
↓
STDO
4.5
20.6
4.5
23.8
ns
In most applications, the node to which PTDO is connected has a pullup resistor. In such cases, this parameter is not significant.
In most applications, the node to which STDO is connected has a pullup resistor. In such cases, this parameter is not significant.
§ This parameter applies only in case of protocol result HARD ERROR.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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