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參數(shù)資料
| 型號(hào)： | SMJ320C31KGDM40B |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-BIT, 40 MHz, OTHER DSP, UUC132 |
| 封裝： | DIE |
| 文件頁數(shù)： | 37/59頁 |
| 文件大小： | 1236K |
| 代理商： | SMJ320C31KGDM40B |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
changing the peripheral pin I/O modes
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa.
timing requirements for peripheral pin changing from general-purpose output to input mode
(see Note 6 and Figure 30)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
84
th(H1H)
Hold time, peripheral pin after H1 high
13
10
8
ns
85
tsu(GPIO-H1L)
Setup time, peripheral pin before H1 low
9
8
ns
86
th(H1L-GPIO)
Hold time, peripheral pin after H1 low
0
ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
86
85
84
Value on Pin
Seen in
Peripheral-
Control
Register
Synchronizer Delay
Buffers Go
From
Output to
Input
Execution
of Store of
Peripheral-
Control
Register
Data Bit
Peripheral
Pin
(see Note A)
I/O
Control Bit
H1
H3
Output
Data
Seen
Data
Sampled
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 30. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
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